Semiconductor Memory Repair Circuit for Double Column Testing
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in performing a test operation using double column lines after a repair operation, as they often interrupt the decoding process when a column is determined defective, limiting simultaneous testing of remaining columns.
Innovation Solution
A semiconductor memory device with a repair circuit that includes a normal decoder, comparison unit, and redundancy decoder, allowing for decoding of input addresses and generating column repair signals to access redundancy column lines, and a duplication control unit to manage access to normal column lines based on repair signals, enabling continued test operations even after repair.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the normal decoder interrupts decoding operation when a defective column is detected, then the reliability of memory access is improved, but the productivity of test operations is reduced because remaining columns cannot be tested simultaneously
Solution Approach 1:
The patent segments the column address decoding into two independent paths: a normal decoder for non-defective columns and a redundancy decoder for defective columns. The comparison unit divides column addresses into defective and non-defective groups, allowing parallel processing of different column segments without mutual interference, thus enabling simultaneous testing of remaining columns while maintaining access reliability.
Solution Approach 2:
The comparison unit acts as an intermediary between the address input and the decoders. It receives column addresses, compares them against stored defective column information, and routes addresses to either the normal decoder or redundancy decoder based on the comparison result. This intermediary function enables intelligent address routing that maintains reliability while preserving test productivity.
2Reliability
If the normal decoder is deactivated when a column repair signal is activated, then the reliability of accessing repaired columns is improved, but the versatility of the system is reduced because test operations using double column lines are interrupted
Solution Approach 1:
The system dynamically adjusts decoder activation based on the type of operation being performed. During normal operation, the normal decoder is deactivated when a column repair signal is activated to ensure reliable access to repaired columns. During test operations, both decoders can be activated simultaneously to enable double column line testing. This dynamic control allows the system to adapt its behavior to different operational modes, maintaining both reliability and versatility.
3Manufacturing precision
If all column addresses are compared with repair addresses, then the manufacturing precision of defect detection is improved, but the loss of time increases because it prevents simultaneous testing of multiple columns
Solution Approach 1:
The comparison unit segments the column address comparison process by dividing addresses into defective and non-defective groups based on comparison with stored repair addresses. This segmentation allows parallel processing: addresses matching defective patterns are routed to the redundancy decoder while non-matching addresses are routed to the normal decoder, enabling simultaneous testing of multiple columns without sacrificing defect detection accuracy.
Data Source
AI summary
A repair circuit includes a normal decoder suitable for decoding partial input addresses of input addresses in response to a first control signal, a comparison unit suitable for comparing the partial input addresses and partial repair addresses of repair addresses in response to a second control signal, and generating a column repair signal when the partial input addresses and the partial repair addresses correspond to each other, and a redundancy decoder suitable for decoding the repair addresses in response to the column repair signal.