Differential Compute-in-Memory Bitcell for Deep Learning
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Solution Overview
Problem
In machine learning applications, particularly in deep learning, the Von Neumann architecture's data-movement bottleneck hinders processing speed, and conventional compute-in-memory architectures face challenges in efficiently handling neuron bias and signal-to-noise ratio in convolutional layers.
Innovation Solution
A differential compute-in-memory bitcell design is introduced, featuring cross-coupled inverters, transmission gates, and capacitors that provide a differential filter output voltage, removing neuron bias and improving signal-to-noise ratio through a multiply-and-accumulate circuit that performs multiplications and accumulations within memory, using pre-charge phases to manage bit lines and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional compute-in-memory architectures are used, then data processing is distributed across bitcells to address the data-movement bottleneck, but neuron bias and signal-to-noise ratio issues hinder processing quality
Solution Approach 1:
The bitcell is divided into two symmetric halves, each with its own inverter and capacitor. The first half processes the positive read bit line while the second half processes the negative read bit line. This segmentation allows independent processing of differential signals, eliminating neuron bias while maintaining high processing speed through parallel operation.
Solution Approach 2:
The patent implements a differential architecture where the second inverter and capacitor act as a counterbalance to the first. The symmetric structure with complementary read bit lines (positive and negative) creates a balanced system that cancels out bias and noise, improving signal-to-noise ratio while maintaining computational efficiency.
2Reliability
If differential architecture is implemented with cross-coupled inverters and capacitors, then neuron bias is removed and signal-to-noise ratio is improved, but device complexity increases
Solution Approach 1:
The cross-coupled inverter structure serves multiple functions: it acts as a storage element for the filter weight bit, a processing element for the multiply-and-accumulate operation, and a differential signal generator. The capacitors simultaneously store charge representing binary values and participate in the analog computation process, reducing the need for separate components.
Solution Approach 2:
The patent merges digital and analog functions within the same bitcell structure. The cross-coupled inverters and capacitors that traditionally store binary data are also used to perform analog multiply-and-accumulate operations. The read bit lines directly interface with the capacitor nodes, combining data retrieval and computation in a single integrated structure.
Data Source
AI summary
A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a positive capacitor. A first plate of the positive capacitor connects to a positive read bit line. An inverter inverts a voltage of the second plate of the positive capacitor to drive a first plate of a negative capacitor having a second plate connected to a negative read bit line.