Write Disturb Detection Circuit for Multi-Port Memory Cells
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Solution Overview
Problem
In multi-port memory cells, dummy read operations from one port can disturb write operations on another port, prolonging write times and increasing the load on storage nodes, which existing detection methods fail to address efficiently.
Innovation Solution
A write disturb detect circuit that utilizes word lines of corresponding memory cells to detect the disturbance condition, using less space and reducing setup time for clock signals compared to other approaches, effectively identifying when a write disturb occurs by monitoring the activation of both word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dummy read operation is performed on port P_B, then the memory cell can be in read-like condition for signal testing, but the write operation on port P_A is disturbed and write time is prolonged
Solution Approach 1:
The patent performs a preliminary check by activating the word line for the write port (P_A) before the actual write operation to detect whether a dummy read is simultaneously occurring on the other port (P_B). If both word lines are activated, the circuit generates a disturb detect signal that allows the memory system to postpone or cancel the write operation, preventing write disturb before it occurs.
2Adaptability or versatility
If dummy read operation is performed on port P_B, then signal testing can be conducted, but the load on storage node increases
Solution Approach 1:
The patent implements a feedback mechanism where the disturb detect circuit continuously monitors the activation state of both word lines and provides real-time feedback about write disturb conditions. When a disturb condition is detected, this feedback signal enables the memory controller to adjust its operation, such as postponing the write or read operation, thereby reducing the harmful load on the storage node that would otherwise occur during dummy read operations.
3Measurement precision
If match address circuitry is used to detect write disturb condition, then the disturbance can be identified, but the circuit occupies more space and has longer setup time
Solution Approach 1:
The patent extracts the essential detection function from complex match address circuitry by using only the word line activation signals, which are already present in the memory system. Instead of comparing full address signals, the invention monitors whether both word lines (WL_A and WL_B) are simultaneously activated, which is sufficient to detect write disturb conditions. This extraction approach maintains detection accuracy while significantly reducing circuit complexity and space requirements.
Data Source
AI summary
A circuit includes a memory cell having a first control line and a second control line, the first control line carrying a first control signal, the second control line carrying a second control signal. A first circuit is coupled to the first control line, the second control line, and a node, and a second circuit is coupled to the node and responds to a timing of the first control signal and the second control signal. The first circuit and the second circuit, based on the first control signal and the second control signal, are configured to generate a node signal on the node, and a logical value of the node signal indicates a write disturb condition of the memory cell.