3D Switched Capacitor Circuit Layout for High-Current CPU Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing power demand from modern central processing units (CPUs) poses a challenge in designing compact and high-density power converters that can meet the escalated current requirements while minimizing circuit area.
Innovation Solution
The apparatus comprises a first device layer with first switches, a second device layer with second switches, and a third device layer between them, featuring first capacitors. The switches are interconnected with the capacitors to form a switched capacitor circuit, which transitions between states in response to switching, enabling efficient power conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional power converter designs are used, then current requirements can be met, but the circuit area becomes excessively large
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture with multiple device layers (first device layer, second device layer, and third device layer) positioned at different vertical levels. This dimensional change allows circuit elements to be arranged in the vertical dimension rather than only horizontally, thereby increasing current capacity without proportionally increasing the horizontal circuit area.
Solution Approach 2:
The power converter circuit is segmented into multiple functional device layers, with switches and capacitors distributed across different layers. The first device layer contains first switches, the second device layer contains second switches, and the third device layer contains first capacitors. This segmentation allows for optimized spatial arrangement and interconnection of circuit elements, achieving high current density in a compact footprint.
2Area of stationary object
If circuit area is reduced to achieve compact design, then power density increases, but manufacturing complexity increases
Solution Approach 1:
By utilizing the vertical dimension with stacked device layers, the patent achieves circuit area reduction without proportionally increasing manufacturing complexity. The layered structure provides clear spatial separation of different circuit functions, making the fabrication process more systematic and manageable compared to attempting to pack all elements into a single planar layer.
Solution Approach 2:
The patent implements a nested hierarchical structure where device layers are stacked and interconnected. The first device layer, second device layer, and third device layer are nested in the vertical dimension with interconnection structures linking corresponding elements across layers. This nesting approach organizes complex circuitry into manageable hierarchical units, facilitating the manufacturing process.
Data Source
AI summary
Disclosed embodiments may include an apparatus including a first device layer including first switches, a second device layer including second switches, and a third device layer disposed between the first device layer and the second device layer. The third device layer includes first capacitors. The first switches and the second switches are interconnected with the first capacitors to form a switched capacitor circuit. The switched capacitor circuit is configured to transition between at least two states in response to switching of the first switches and the second switches.