Switched Capacitor Networks TRIZ Cases

Non-reciprocal circulators and reflective N-path filter elements enable wideband RF reconfiguration with linear filtering and selective path control.

Stacked switch and capacitor layers shrink converter area while delivering the high current modern CPUs require.

Mirrored current pulses cancel switched-capacitor ripple on voltage lines, improving regulator stability without larger load capacitance.

Charge diffusion across sampled capacitors enables analog Gaussian filtering with adjustable bandwidth while avoiding large RC components for slow signals.

A filter removes induced transmit signals in a dual RF path, preserving port isolation and reception quality during simultaneous transmission.

Switched-capacitor aliasing extends RF delay beyond 5 ns at high frequency while avoiding bulky cable spools and power-hungry conversion stages.

A consolidated N-order filter cuts op-amp count to reduce circuit area, power use, and harmonic interference while preserving audio signal linearity.

A level-shifting capacitor array adjusts equivalent capacitance to compensate DC gain drift and keep switched-capacitor loop gain stable.

Pre-feeding the input voltage to the second switched-capacitor stage cuts signal delay and improves turn-on speed in a series switching circuit.

Switchable coupling between baseband filter stages improves stopband rejection and noise reduction across 5G NR, 4G, and GSM without extra IC area.

Two sampling capacitors alternate with one amplifier to double analog data rate while avoiding the extra power draw of dual-amplifier circuits.

Switchable single-pole and complex-pole baseband filtering improves stopband rejection and noise control without increasing IC footprint.

A switched-capacitor glitch filter uses reset stages to suppress burst glitches under 50 ns while avoiding RC time-constant variation.

A charge compensation circuit shares capacitor charging with reference buffers to speed settling and cut power in capacitive DACs.

Low-pass and anti-aliasing filters in the DC discharge path keep MEMS gyroscope sense amplifiers linear while rejecting resonant noise.

A step detector bypasses filtering during large input changes, cutting filter delay while preserving signal quality in normal operation.

A replica reference and compensation circuit supplies switching charge locally, cutting reference-source load, ripple, and settling time.

Resistor-assisted switched-capacitor feedback and a non-50% clock duty cycle sharpen roll-off and stabilize DC gain and frequency across corners.

Alternating capacitor sampling and simultaneous charge averaging remove unwanted ripple while cutting capacitor area, buffer needs, and offset.

Capacitor stacking and bottom-plate sampling isolate common modes in cascaded MDAC stages, cutting noise, power, and level shifter complexity.

Additional FETs let a compact signal averager switch with switched capacitor filtering, extending dynamic range and suppressing noise.

A switched-capacitor high-pass filter adapts impedance and signal weighting to cut path-transition artifacts while preserving ADC dynamic range.

Switched capacitor and resistor tuning preserves RF input coupling and linearity while cutting DC power in ultra-low-power receiver front ends.

Digitally controlled switched capacitors let one analog block switch between single-ended and differential functions, saving chip area.

Weighted accumulation turns capacitance sensing into FIR filtering, improving touch input detection by rejecting noise interference.

A compensation circuit supplies switching charge locally, cutting reference generator power, voltage ripple, and settling time.

Periodic MOSFET turn-on keeps drain and source voltages close, reducing input distortion when programmable capacitance is unloaded.

Uses an on-chip DAC and amplifier to test differential ADCs in-system, reducing reliance on factory equipment while checking gain error and INL.

Relocating the impedance conversion circuit after the amplifier blocks clock leakage and preserves flat passband response with strong out-of-band attenuation.

A bandwidth compensation network senses SCN and output signals to widen charge-domain filter bandwidth and reduce folding noise distortion.

Periodic MOSFET gate control keeps drain voltage near source voltage, reducing off-state distortion in programmable capacitor arrays.

Programmable delay and power sensing help a charge-domain filter correct process-driven bandwidth shifts and remove Sinc-function distortion.

A switched-capacitor low-pass filter adjusts dominant pole frequency to improve monitoring speed, ADC range use, and precision.

Frequency-selective degeneration lets one active RF filter replace SAW and BAW filters, improving linearity, sensitivity, and front-end integration.

Dedicated sampling and sensing phases cancel offset and low-frequency noise in switched-capacitor stages without disturbing phase control.

A differential amplifier switches between differential and single-ended outputs without reconfiguring switched-capacitor networks or changing response.

Programmable delay and power-reference feedback reshape charge-domain filter response to widen bandwidth and reduce Sinc distortion.

Parallel charge averaging lets a switched capacitor notch filter cut offset, distortion, and circuit area without large capacitors or buffers.

Clocked sampling and output isolation improve notch frequency accuracy, cut power use, and reduce noise in integrated filter circuits.

Selective coupling lets baseband filters share active and passive components across 5G NR, 4G, and GSM channels while limiting IC area and noise.

Cascade delay circuits stabilize RFID power supply against temperature variations, enabling reliable FRAM memory operation.

A sample-and-hold notch filter synchronizes with chopper switching to remove ripple from differential outputs.

A switched-capacitor filter analog switch maintains MOS FET substrate potentials at a common reference voltage to eliminate external leakage currents.

A small capacitance compensation network circuit uses switch modules to charge and discharge capacitors, generating an error signal.

A multiplexed multilevel converter amplifier synchronizes supply voltage levels with output signals.

Gate boosted switches maintain transistors within the linear region, preventing gate dielectric stress while enabling user-selectable filter bandwidth.