Passive Switched Capacitor MDAC Topology for Common-Mode Isolation
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Solution Overview
Problem
Pipelined ADCs face challenges in designing passive switched capacitor (PSWC) circuits for cascaded stages, particularly in achieving compatible common modes and minimizing noise and complexity, especially in smaller process nodes like 28 nm, which complicates the circuit design and requires additional components like level shifters that can attenuate signals and increase noise.
Innovation Solution
A PSWC circuit with charge pump gain is introduced, utilizing bottom plate sampling and capacitor stacking to decouple common modes, allowing for reduced noise, lower power consumption, and simplified architecture, eliminating the need for level shifters and complex buffers, thereby enhancing compatibility and performance in cascaded stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional PSWC circuits are used in cascaded stages, then signal amplification is achieved, but common mode compatibility becomes difficult and noise increases
Solution Approach 1:
The circuit is segmented into separate common mode domains using capacitors and switches. Each domain (input common mode, DAC common mode, output common mode) is independently controlled, allowing signal amplification while isolating noise sources and maintaining common mode compatibility across cascaded stages.
Solution Approach 2:
Capacitors are introduced as intermediary elements between different common mode domains. These capacitors act as mediators that couple the domains while allowing independent common mode control, thereby achieving signal amplification without direct noise coupling between stages.
2Adaptability or versatility
If level shifters are added to achieve common mode compatibility, then compatibility is improved, but circuit complexity and noise increase
Solution Approach 1:
The capacitors and switches in the circuit serve multiple functions: they provide common mode isolation, enable signal amplification, and facilitate cascaded stage connection. This multi-functionality achieves common mode compatibility without requiring additional level shifter components, thereby reducing overall circuit complexity.
Solution Approach 2:
The PSWC circuit inherently provides common mode compatibility through its capacitor-based architecture. The circuit structures itself to create isolated common mode domains that are naturally compatible with cascaded stages, eliminating the need for external level shifter components and reducing design complexity.
3Adaptability or versatility
If level shifters are added to achieve common mode compatibility, then compatibility is improved, but signal attenuation and noise increase
Solution Approach 1:
Capacitors serve as intermediary elements that couple different common mode domains without the signal attenuation and noise introduction associated with level shifter circuits. The capacitive coupling maintains signal integrity while achieving common mode compatibility across cascaded stages.
4Adaptability or versatility
If additional components like level shifters are added, then common mode compatibility is achieved, but area and power consumption increase
Solution Approach 1:
The existing capacitors and switches in the PSWC circuit are made multi-functional, serving both their original signal processing roles and common mode isolation roles. This eliminates the need for additional level shifter components, thereby reducing the overall circuit area while achieving common mode compatibility.
Solution Approach 2:
The circuit uses its inherent capacitive elements to provide common mode isolation and compatibility. By making the existing components self-sufficient for multiple functions, the design avoids adding extra components, thus minimizing circuit area while achieving the desired compatibility.
5Adaptability or versatility
If additional components like level shifters are added, then common mode compatibility is achieved, but power consumption increases
Solution Approach 1:
The capacitors and switches perform multiple functions including signal amplification and common mode isolation. This eliminates the need for additional power-consuming level shifter components, thereby reducing overall power consumption while achieving common mode compatibility.
Solution Approach 2:
The circuit's existing components provide common mode isolation without requiring additional active components that would consume extra power. The capacitive architecture inherently enables compatibility across cascaded stages, reducing the power budget required for common mode management.
Data Source
AI summary
In pipelined analog-to-digital converters (ADCs), a passive switched capacitor (PSWC) circuit can be used in a multiplying analog-to-digital converter (MDAC), which generates an analog output being fed to a subsequent stage. Complementary analog input signals are sampled respectively onto first and second capacitors, which are stacked to provide gain. The first capacitor is positioned between a first input switch and an output node of the PSWC circuit, and the second capacitor is positioned between the second input switch and a digital-to-analog converter (DAC) output. The topology advantageously isolates common modes of the complementary analog input signals, the DAC output, and the output of the PSWC circuit. As a result, the topology offers more degrees of freedom in the overall circuit design when stages having the MDAC are cascaded, resulting in pipelined ADCs with a more elegant design with lower noise and lower power consumption.