Capacitive DAC Charge Compensation for Faster Settling
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Solution Overview
Problem
Switched capacitor circuits face challenges in reducing settling time and power consumption due to the high output capability requirements of reference buffers, which increases design complexity and power consumption.
Innovation Solution
Incorporating a charge compensation circuit that supplies or releases electric charges to the output capacitor, reducing the burden on reference buffers by providing partial charge requirements, thus enhancing settling speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the reference buffer is designed with higher output capability to reduce settling time, then the settling speed of the switched capacitor circuit is improved, but the power consumption increases
Solution Approach 1:
The charge supply function is segmented between the reference buffer and the charge compensation circuit. The charge compensation circuit handles the bulk charge transfer during switching transitions, while the reference buffer only needs to maintain voltage levels, dividing the workload and reducing the power consumption burden on the reference buffer while maintaining fast settling speed.
Solution Approach 2:
The charge compensation circuit acts as an intermediary between the power supply and the output capacitor. It provides additional charge paths that supplement the reference buffer, enabling faster charge transfer without requiring the reference buffer to operate at high current levels, thus reducing its power consumption while improving settling speed.
2Loss of time
If the reference buffer is designed with higher output capability to reduce settling time, then the settling time is reduced, but the design complexity increases
Solution Approach 1:
The function of rapid charge transfer is segmented from the reference buffer and assigned to the charge compensation circuit. This allows the reference buffer to be designed with simpler, lower-power components while the charge compensation circuit handles the complex switching and charge transfer operations, distributing the design complexity across specialized blocks rather than concentrating it in the reference buffer.
Solution Approach 2:
The charge compensation circuit serves as an intermediary that simplifies the reference buffer design by taking over the complex charge transfer tasks. The reference buffer only needs to perform simple voltage buffering, while the charge compensation circuit handles the complex switching and charge management, reducing the design complexity of the critical reference buffer component.
3Power
If the reference buffer supplies all charges for charging or discharging the output capacitor, then the output capability requirement is high, but the charge compensation circuit provides alternative charge paths to reduce this burden
Solution Approach 1:
The charge supply responsibility is segmented between multiple sources: the reference buffer provides baseline charge and maintains voltage levels, while the charge compensation circuit provides additional charge paths for rapid charge transfer. This segmentation reduces the output capability requirement of the reference buffer while maintaining overall system performance.
Solution Approach 2:
The invention changes the operational parameters of the reference buffer by introducing the charge compensation circuit. The reference buffer operates at lower current levels and power consumption because the charge compensation circuit handles the high-current charge transfer tasks, effectively changing the operating point and design requirements of the reference buffer.
Data Source
AI summary
A switched capacitor circuit includes an output capacitor, a first transmission switch, a first reference buffer, a second transmission switch, a second reference buffer and a charge compensation circuit. The output capacitor includes a first terminal and a second terminal, wherein the first terminal is coupled to an output terminal of the switched capacitor circuit, and the second terminal is coupled to a reference node. The first transmission switch is coupled to the reference node. The first reference buffer is coupled to the first transmission switch. The second transmission switch is coupled to the reference node. The second reference buffer is coupled to the second transmission switch. The charge compensation circuit is coupled to the reference node.