Programmable Alias Delay Circuit for Long RF Delay at High Frequency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay devices struggle to achieve nanosecond delays at high frequencies without significant power consumption or physical bulk, limiting their application in radar testers, digital RF memory, and active RFID tagging devices.
Innovation Solution
A programmable alias delay device using switched capacitors with aliasing techniques, employing input and output filters, and a programmable delay stage with reduced sampling rates to achieve delays exceeding 5 ns at frequencies over 2 GHz, utilizing a multi-stage switched-capacitor architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If traditional delay devices are used to achieve nanosecond delays at high frequencies, then the delay requirement is met, but the device requires downconversion and upconversion which consumes significant power
Solution Approach 1:
The patent replaces traditional mechanical/electronic delay devices that require downconversion and upconversion with a switched-capacitor based delay device that operates directly at RF frequencies. This substitution eliminates the need for frequency conversion stages, thereby significantly reducing power consumption while achieving the same delay function.
Solution Approach 2:
The patent changes the operating parameters of the delay device by using switched-capacitor technology that can operate directly at high RF frequencies (up to 2 GHz and beyond) without requiring frequency conversion. This parameter change enables the device to achieve nanosecond delays at the original RF frequency, avoiding the power-consuming downconversion and upconversion processes.
2Duration of action of moving object
If coaxial or optical cable spools are used to achieve delays in excess of 10 ns at frequencies greater than 2 GHz, then the delay requirement is met, but the physical size becomes large and limited to laboratory environment
Solution Approach 1:
The patent replaces physical cable spools (coaxial or optical) with an integrated switched-capacitor delay device that can be implemented on a semiconductor chip. This substitution transforms a bulky mechanical delay system into a compact electronic device, reducing the physical size from meters to millimeters while maintaining the same delay function at high frequencies.
Solution Approach 2:
The patent transitions the delay function from a spatial dimension (long cable spools extending through space) to a temporal dimension achieved through switched-capacitor sampling and holding mechanisms. This dimensional change allows the same delay function to be achieved in a compact form factor suitable for integration into portable and space-constrained applications.
3Duration of action of moving object
If gm-C all-pass filters are used to achieve delay at RF, then the delay is achieved, but the device is limited to frequencies of less than 2.5 GHz
Solution Approach 1:
The patent changes the fundamental operating parameters by using switched-capacitor technology that can operate at frequencies well beyond 2.5 GHz (up to 2 GHz and higher in various embodiments). This parameter change overcomes the frequency limitation of gm-C all-pass filters while maintaining the ability to achieve nanosecond delays at the higher operating frequencies.
Solution Approach 2:
The patent employs dynamic switching mechanisms in the switched-capacitor delay device that enable operation at high frequencies. The rapid switching of capacitors allows the device to maintain its delay function at frequencies exceeding 2.5 GHz, where traditional gm-C all-pass filters become ineffective due to their inherent frequency limitations.
4Speed
If LC artificial delay lines are used as true-time delay devices, then the device may be used at frequencies exceeding 12 GHz, but the delay is limited to less than 550 ps due to large physical size
Solution Approach 1:
The patent transforms the delay mechanism from a spatially-extensive LC artificial delay line to a temporally-based switched-capacitor sampling system. This dimensional change allows the device to achieve much longer delay times (nanoseconds rather than picoseconds) without requiring proportionally larger physical size, thereby overcoming the trade-off between delay duration and physical dimensions at high frequencies.
Solution Approach 2:
The patent segments the delay function into multiple switched-capacitor stages that can be cascaded to achieve longer total delays. Each stage contributes a portion of the total delay, and by combining multiple stages, the device can achieve nanosecond delays at frequencies exceeding 12 GHz without requiring the large physical size of traditional LC artificial delay lines.
Data Source
AI summary
A programmable alias delay device providing output in a desired frequency band and a maximum delay of >5 ns over a broad bandwidth and at a high frequency is disclosed. The device includes an input bandpass filter and an input stage with M sampling switched capacitor elements, reducing the sampling rate by M. The device includes a programmable delay stage with M programmable switched capacitor banks, each bank having N delay switched capacitor storage elements, reducing the sampling rate by M×N. This reduced sampling rate permits smaller sampling switches, with reduced leakage current and longer programmable delay times. The device includes an output reconstruction stage that reconstructs a delayed version of the input signal by combining signals from the programmable delay stage. Using a subsequent output alias filter, an alias band in the desired frequency band is selected and output.