3D Transistor Structure With Central Pole for Leakage Suppression
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Solution Overview
Problem
Conventional transistor structures face challenges in reducing standby current (IOFF) and leakage current due to scaled-down dimensions, leading to increased gate-induced drain leakage and short channel effects, making it difficult to achieve Tera-Scale Integration (TSI) with billions of transistors on a die.
Innovation Solution
A 3D transistor structure is introduced, featuring a substrate with a convex conductive channel region, a central non-conductive pole, and isolation walls to clamp the active region, reducing leakage current and improving channel control, with the central pole made of oxide thermally grown in a trench and surrounded by a silicon ring, and the use of selective growth semiconductor layers to enhance fin width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to increase integration capacity, then the number of transistors per die increases, but standby current (IOFF) and leakage current increase
Solution Approach 1:
The channel region is segmented into multiple sub-channels separated by insulating membranes, which divide the leakage current path into multiple isolated segments. This segmentation prevents continuous leakage current flow while maintaining the scaled-down transistor dimensions needed for high integration capacity.
Solution Approach 2:
Insulating membranes are strategically placed at specific locations within the channel region where leakage current tends to concentrate. This local quality enhancement targets the problematic areas without affecting the overall transistor performance, reducing IOFF while maintaining integration density.
2Productivity
If transistor dimensions are scaled down, then integration capacity increases, but gate-induced drain leakage and short channel effects worsen
Solution Approach 1:
The insulating membranes extend vertically into the channel region, adding a vertical dimension to the leakage blockage mechanism. This vertical extension creates multiple barriers that gate-induced drain leakage must overcome, effectively suppressing short channel effects even at scaled-down dimensions.
Solution Approach 2:
The insulating membranes act as intermediary structures between the source and drain regions, providing physical and electrical separation that prevents direct leakage paths. These membranes mediate the interaction between the gate and drain, reducing gate-induced drain leakage while maintaining transistor functionality.
3Ease of manufacture
If conventional FinFET structures are used, then manufacturing capability is maintained, but leakage current paths within the fin structure increase
Solution Approach 1:
Insulating membranes are extracted or removed from specific regions within the fin structure to create isolated channel segments. This selective removal eliminates continuous leakage current paths while preserving the FinFET manufacturing process and overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The new structure achieves a significant reduction in standby current by 10 to 100 times, lowering leakage current to less than 1 pA and improving gate-induced drain leakage and short channel effects, enabling more efficient integration of transistors on a die.
Implementation Method 1
the central pole made of oxide thermally grown in a trench
Data Source
AI summary
A transistor structure includes a substrate, a source region, a drain region, a trench, and a central pole. The substrate has a convex structure, wherein the convex structure has a conductive channel region. The source region contacts with a first end of the conductive channel region. The drain region contacts with a second end of the conductive channel region. The trench is formed in the convex structure and between the first end and the second end. The central pole is formed in the trench, wherein a material of the central pole is different from that of the conductive channel region.