3D Transistor Stacking with Silicide Coupling
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Solution Overview
Problem
Current semiconductor fabrication techniques face challenges in scaling transistors to single-digit nanometer nodes, particularly in achieving high transistor density in planar devices, and applying 3D integration to logic chips is more complex compared to flash memory applications.
Innovation Solution
A method for fabricating 3D semiconductor apparatuses involving a multilayer stack of selectively etchable dielectric materials, forming vertical channels, and coupling them with silicide to create a 3D stack of NMOS and PMOS devices, enabling 360-degree access for optimal routing and significant device scaling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If 2D planar fabrication is used to scale transistors, then manufacturing processes are relatively simple, but transistor density per unit area reaches scaling limitations at single-digit nanometer nodes
Solution Approach 1:
The patent transitions from 2D planar transistor fabrication to 3D vertical stacking by forming multiple semiconductor devices stacked vertically on a single substrate. This dimensional change allows transistor density to scale by utilizing the third dimension (vertical height) rather than being constrained to two-dimensional area scaling, thereby overcoming the density limitations of conventional 2D fabrication at single-digit nanometer nodes.
2Productivity
If 3D vertical stacking is implemented, then transistor density in volume increases, but fabrication process complexity and difficulty increase significantly
Solution Approach 1:
The patent divides the 3D stacking fabrication into distinct segments: forming a multilayer dielectric stack with selectively etchable layers, creating openings through the stack, forming vertical channels, selectively removing transition dielectric layers, and forming silicide connections. This segmentation of the complex 3D fabrication process into manageable sequential steps makes the manufacturing more controllable and easier to execute despite the increased dimensional complexity.
Solution Approach 2:
The patent performs preliminary actions by first forming the complete multilayer dielectric stack with selectively etchable transition layers before forming the vertical channels. This preliminary structuring of the dielectric layers with built-in selectivity enables subsequent selective removal of transition layers to create silicide connections, simplifying the overall fabrication sequence and improving manufacturability.
3Reliability
If transition dielectric layers are removed to enable silicide coupling, then vertical channel connectivity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces transition dielectric layers as intermediary materials between different dielectric layers in the stack. These transition layers are specifically designed to be selectively removable, serving as temporary spacers or isolation barriers during fabrication. By removing these intermediary transition layers, the patent enables direct silicide coupling between vertically stacked channels while maintaining manufacturing precision through the selective etchability of the transition layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of densely packed 3D transistors with reduced layout and enhanced scaling capabilities, facilitating the development of advanced logic chips by enabling vertical stacking of CMOS devices with efficient routing and increased transistor density.
Implementation Method 1
forming a silicide at the uncovered portion to couple the first channel to the second channel
Implementation Method 2
removing a transition dielectric layer of the multilayer stack such that a portion of the first channel and the second channel that interfaces at the transition dielectric layer is uncovered
Data Source
AI summary
Aspects of the present disclosure provide 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including first S/D regions, a first gate region sandwiched by the first S/D regions, and a first channel surrounded by the first S/D regions and the first gate region; a second semiconductor device stacked on the first semiconductor device that includes second S/D regions, a second gate region sandwiched by the second S/D regions, and a second channel surrounded by the second S/D regions and the second gate region and formed vertically in-situ on the first channel; and silicide formed between the first and second semiconductor devices where the first and second channels interface and coupled to an upper one of the first S/D regions of the first semiconductor device and a lower one of the second S/D regions of the second semiconductor device.