3D Vertical Transistor Contacts With Silicide Routing
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Solution Overview
Problem
The challenge in semiconductor device fabrication lies in achieving three-dimensional (3D) integration of transistors to overcome scaling limitations and address issues like leakage currents and short-channel effects, particularly in logic chips where forming electrical contacts for flexible routing and maintaining electrical continuity is difficult.
Innovation Solution
The solution involves fabricating 3D microelectronic devices with 360-degree metal contact routing for source, drain, and gate contacts using 3D salicidation techniques, where metal silicide layers are formed through annealing, enabling enhanced conductivity and performance by allowing multiple metal types in a single process step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 3D integration of transistors is implemented to overcome scaling limitations, then transistor density is improved, but difficulty in forming electrical contacts and maintaining electrical continuity worsens
Solution Approach 1:
The patent transitions from planar 2D contact formation to 3D contact formation by growing semiconductor structures vertically. Multiple metal layers are formed at different vertical levels, allowing electrical contacts to be established in three dimensions. This enables continuous electrical pathways through the vertically stacked transistor architecture while maintaining flexibility in routing contacts to source, drain, and gate regions.
Solution Approach 2:
The patent divides the contact formation process into multiple discrete metal layers (first metal layer, second metal layer, third metal layer) that can be independently formed and positioned. Each metal layer serves specific contact functions, allowing separate optimization of contact formation to different transistor regions (source, drain, gate) without interfering with other contacts.
2Reliability
If multiple metal types are used in 3D salicidation for enhanced conductivity, then electrical performance is improved, but process complexity worsens
Solution Approach 1:
The patent applies different metal materials to different spatial locations and contact regions based on specific electrical performance requirements. First metal, second metal, and third metal are selectively positioned in different vertical layers and contact regions, allowing optimization of conductivity and electrical characteristics for each specific contact path while maintaining overall process integration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases transistor density, enhances 3D conductivity, and improves performance by enabling precise control over 3D salicidation through 360-degree ALD deposition, allowing for efficient electrical contact formation in vertically stacked transistors.
Implementation Method 1
The method can anneal the silicide metal above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer
Implementation Method 2
The method can include forming a vertical channel structure within the opening by epitaxial growth
Data Source
AI summary
Structures and methods are disclosed in which a layer stack can be formed with a plurality of layers of a metal, where each of the layers of metal can be separated by a layer of a dielectric. An opening in the layer stack can be formed such that a semiconductor layer beneath the plurality of layers of the metal is uncovered. One or more vertical channel structures can be formed within the opening by epitaxial growth. The vertical channel structure can include a vertically oriented transistor. The vertical channel structure can include an interface of a silicide metal with a first metal layer of the plurality of metal layers. The interface can correspond to one of a source or a drain connection of a transistor. The silicide metal can be annealed above a temperature threshold to form a silicide interface between the vertical channel structure and the first metal layer.