3D IC Package with Stacked TVS Chip for ESD Protection
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Solution Overview
Problem
Traditional 2D IC packages face issues with ESD protection due to bond wire inductances, which can damage functional chips before TVS chips activate, and require complex fabrication processes to adjust TVS characteristics, increasing costs and degrading performance.
Innovation Solution
A 3D IC package design where IC and TVS chips are stacked on a substrate with conduction plugs, eliminating bond wire inductances and allowing independent fabrication processes for each chip, enabling easier adjustment of TVS electrical characteristics and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bond wire connections are used to connect IC chip and TVS chip in traditional 2D package, then the TVS chip can provide ESD protection, but the bond wire inductance degrades the protection capability and may damage the functional chip before TVS activation
Solution Approach 1:
The patent transitions from a traditional 2D planar arrangement to a 3D stacked configuration. The IC chip and TVS chip are vertically stacked and interconnected through through-silicon-via (TSV) technology, eliminating the need for long bond wire connections. This dimensional change reduces the inductance of interconnect paths, enabling faster ESD response and improved protection capability.
Solution Approach 2:
The patent merges the IC chip and TVS chip into a single integrated 3D package structure. Both chips are closely stacked and interconnected, creating a unified system where the TVS chip can immediately respond to ESD events without the delay introduced by external bond wire connections. This integration enhances the overall reliability of ESD protection.
2Adaptability or versatility
If TVS characteristics are adjusted by changing fabrication process for IC chip, then the TVS electrical characteristics can be modified, but the fabrication cost increases and functional chip performance may be degraded
Solution Approach 1:
The patent segments the TVS functionality from the IC chip fabrication process by using a separate TVS chip. This independent TVS chip can be fabricated with optimized processes specifically tailored for ESD protection characteristics, while the IC chip maintains its own fabrication process. This segmentation allows flexible adjustment of TVS electrical characteristics without affecting IC chip manufacturing or increasing overall fabrication costs.
Solution Approach 2:
The patent creates a universal 3D package structure that can accommodate different TVS chip types and configurations. The standardized TSV interconnection methodology allows the same package structure to work with various TVS chips having different electrical characteristics, providing design flexibility without requiring changes to the base fabrication process.
3Ease of operation
If IC chip and TVS chip are arranged in 2D configuration on die paddle, then the package can be assembled, but the parasitic inductance of bond wire reduces protection effectiveness
Solution Approach 1:
The patent employs 3D vertical stacking with TSV interconnections to replace the 2D planar arrangement. This dimensional transformation maintains ease of assembly through standardized stacking processes while dramatically reducing the inductance of inter-chip connections, thereby enhancing ESD protection capability.
Data Source
AI summary
A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.