3D Vertical FeRAM Strings Using Thin HfO2 Ferroelectric Layers
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Solution Overview
Problem
Existing 3-dimensional memory circuits face challenges in achieving high-density, low-power, and low-cost solutions suitable for high-speed storage class memory applications, with current technologies like 3D XPoint and vertical NOR-type memory arrays facing issues such as high manufacturing costs, power consumption, and complex integration.
Innovation Solution
A 3-dimensional vertical memory string array is developed using zirconium-doped or silicon-doped HfO2 ferroelectric materials, combined with a vertical gate electrode, gate oxide layer, and conductive semiconductor regions, forming low-cost, low-power, and high-density ferroelectric field-effect transistor (FET) cells with random-access capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ferroelectric materials (PZT, SBT) are used in FeFET, then dipole moments can be aligned by electric field, but the ferroelectric layer must be at least 70 nm thick which does not provide high-density memory circuits
Solution Approach 1:
The patent changes the material parameter from conventional ferroelectric materials (PZT, SBT) to hafnium oxide-based ferroelectric material, which enables the ferroelectric layer thickness to be reduced from 70 nm to 5-15 nm while maintaining ferroelectric switching capability, thereby achieving high-density memory circuits
2Ease of operation
If 3D XPoint memory circuits are used, then bit-by-bit access is allowed suitable for SCM applications, but cross-point patterning requires double exposures which is prohibitively high in manufacturing cost
Solution Approach 1:
The patent segments the memory structure into vertical channels with gate electrodes wrapped around them, allowing each memory cell to be formed by sequential deposition and etching steps rather than requiring complex cross-point patterning with double exposures, thus reducing manufacturing cost while maintaining random access capability
Solution Approach 2:
The patent transitions from the planar cross-point architecture to a three-dimensional vertical channel structure with gate electrodes surrounding the channels, enabling memory cells to be stacked vertically and accessed through word lines and bit lines in a different spatial configuration that simplifies patterning
3Ease of operation
If 3D XPoint memory circuits based on phase-change material are used, then bit-by-bit access is enabled, but high leakage currents from sneak paths result in high power dissipation
Solution Approach 1:
The patent introduces selector devices (diodes or transistors) as intermediary elements in series with each memory cell to block sneak path currents, allowing only the selected memory cell to conduct during read/write operations, thereby reducing power dissipation while maintaining random access capability
Solution Approach 2:
The patent employs dynamic voltage control where the bit line and word line voltages are switched to different levels during select and non-select periods, enabling the selector device to dynamically open or close the circuit path to prevent leakage currents from unselected cells
4Volume of moving object
If vertical NOR-type memory string arrays are used, then 3-dimensional structure is achieved, but complicated X and Y patterning schemes are required and power consumption is high
Solution Approach 1:
The patent adopts a three-dimensional vertical channel structure where gate electrodes wrap around the channels in the radial direction, allowing memory cells to be stacked vertically along the Z-axis while simplifying the X-Y plane patterning to basic trench formation and electrode deposition, thus reducing patterning complexity compared to NOR architecture
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides high-speed, low-power, and low-cost memory circuits suitable for storage class memory applications with reduced leakage currents and simplified manufacturing processes, enabling efficient bit-by-bit access and low power dissipation.
Implementation Method 1
conventional ferroelectric materials, such as those based on lead zirconate titanate (PZT) and strontium bismuth tantalate (SBT), for example, do not provide high-density memory circuits. This is because the ferroelectric layer in an FeFET based on these materials must at least 70 nm thick.
Implementation Method 2
A 3-dimensional vertical memory string array is developed using zirconium-doped or silicon-doped HfO2 ferroelectric materials, combined with a vertical gate electrode, gate oxide layer, and conductive semiconductor regions, forming low-cost, low-power, and high-density ferroelectric field-effect transistor (FET) cells
Data Source
AI summary
A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low-cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer, and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.