Read-Only Memories TRIZ Cases

Control logic boosts sub-block channels, selectively discharges them by data pattern, and programs multiple cells with one pulse.

Vertical FeRAM strings use doped HfO2 and wrapped gates to support dense, low-power random-access memory.

This memory-chip case detects partially programmed storage spaces and disables error correction to improve reading efficiency and accuracy.

Widened dummy bit lines lower source-voltage path resistance in memory blocks.

This case uses segmented contact plug diameters across gate levels to preserve pad thickness and improve manufacturing reliability.

A lower extra-verify voltage identifies under-programmed cells for selective reprogramming, supporting stable threshold voltages over time.

This memory case zones wordlines by switch size and sets negative bitline bias to support scalable programming.

This case uses separated memory cell blocks and programmed ground select thresholds to improve data reliability at high integration density.

A pre-read kick voltage and separate transistor gate biases improve NAND memory read accuracy despite threshold-voltage variation.

Series selector-resistor cells enable 3D OTP stacking, reliable sensing, and high-density storage without extra fabrication masks.

Dividing NAND blocks along the x-direction enables parallel program or erase operations while inhibiting other sub-blocks.

A source-line discharge transistor uses adaptive gate voltage during program loops to reduce bouncing and improve bit-line current sensing.

This case calibrates read-level offsets by cell state to reduce errors from interference and charge loss in memory arrays.

This memory architecture uses threshold-voltage differences to selectively control shared-bit-line strings and simplify 3D NAND fabrication.

This memory case uses mode-dependent word-line voltage levels and durations to balance speed, reliability, and line load.

Series-parallel memory cells store multi-level data through resistance sensing.

Two-bit storage uses independent MOS breakdown states to strengthen OTP security.

Adjacent pass transistors for same-level word lines reduce wiring variation and loading skew while preserving chip size.

A wide-band-gap oxide transistor and stacked capacitor reduce memory area and off-state current while retaining data after power loss.

The controller counts verification failures and switches between page and byte programming to limit time lost on difficult flash cells.

This case uses multi-loop subgroup counting to keep 3D NAND verification accurate despite differing cell programming speeds.

This memory case uses selective word-line bias ramp rates to speed post-erase defect testing without sacrificing detection accuracy.

A semiconductor memory device links NOR memory and variable-resistor crossbar arrays to shorten AI learning data transfers.

Segmented bank, sector, and row fields simplify decoding for varying sector counts while reducing combinatorial logic and die space.

A vertically stacked memory array and guard ring over the common source tap improve page-buffer integration and chip compactness.

Segmented word line connections reduce gate resistance and parasitic voltage drops.

This memory case stores write temperature data and updates read parameters to reduce bit errors, latency, and error-correction burden.

A source/drain-applied program voltage separates memory-cell current paths, reducing leakage and stress on unselected cells.

This case adjusts flash-memory pass voltage from ISPP and ISPE pulse shifts, preserving threshold control across program/erase cycles.

A first charge stage prepares the sensing node before the bit line is raised, reducing peak current and voltage fluctuations.

Rule-based PV target adjustment balances BER and valley margins across programming distributions to extend memory endurance.

A memory control sequence delays the adjacent top-select gate pulse to limit voltage spikes and leakage during programming.

Intermediate NAND cell patterns guide reference voltage changes during reads, improving accuracy while reducing retry-related overhead lag.

This case uses independently controlled select transistors and Fowler-Nordheim tunneling for selective erase in MTP memory arrays.

A dual-mode readout compares detection currents directly or with reference-current shifts to reduce cell stress and writing time.

Antifuse OTP memory separates programming and read paths to stabilize read current and reduce errors from breakdown variation.

A last-written-page and word-line lookup applies progressive offsets before calibration, protecting data integrity in partial memory blocks.

A prepulse followed by negative bias on unselected string lines reduces read delays from vertical-channel cell variation.

This case places dual-gate IGZO FinFET memory cells in upper metallization layers to increase density without shrinking planar features.

This case shows how NAND memory structures form solenoid inductors, reducing area and manufacturing burden in on-chip power conversion.

A repurposed write-protect pin and timeout circuit reset memory without relying on failed internal controllers or adding a reset pin.

This memory case uses steeper edge-group and gentler center-group voltage slopes to shorten prepulses without raising peak current.

Temperature feedback adjusts under-drive time and offset to stabilize voltage during semiconductor memory read and verify operations.

Charging, discharging, and address-select circuits coordinate shared nodes and vias for precise stacked-cell operations.

A common source line monitor and clock-count mapping adjust NAND flash pass voltage to protect data retention without excessive voltage.

The controller ranks read retry tables by decoding success to reduce failed retries and preserve flash-memory access speed.

Sequential voltage pulses stop current after snapback, then tune resistance memory cells into multiple data states.

A data latch and sensing latch preserve suspend data while enabling host access and efficient normal-operation resumption.

This case uses separate QLC bit positions for valid data and check data, helping correct read errors without sacrificing storage density.

This case shows how ferroelectric polarization and interface charge traps replace high-voltage anti-fuse programming for compact OTP memory.