Memory Chip Programming-State Detection for Selective Error Correction
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Solution Overview
Problem
Existing memory chips face errors during error correction due to multiple programming operations without proper state detection, leading to reduced reading efficiency and accuracy.
Innovation Solution
A method and memory chip design that determines the operating state of storage spaces based on the quantity of written memory units, disabling error correction for part programmed states to enhance reading success rate and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error correction mechanism is always enabled for storage spaces, then data accuracy is improved, but reading efficiency deteriorates due to unnecessary thread operations in part programmed states
Solution Approach 1:
The error correction mechanism is made dynamic by enabling it only when the storage space is in a fully programmed state. The system transitions between enabled and disabled states based on the programming status detection, avoiding unnecessary operations in part programmed states while maintaining data accuracy when needed.
Solution Approach 2:
The system changes the operational parameter of the error correction mechanism based on the storage space state. By detecting whether the storage space is fully programmed or partially programmed, the system adjusts the error correction mechanism's activation status, optimizing both efficiency and accuracy.
2Reliability
If error correction is performed on all storage spaces, then data reliability is improved, but device complexity increases due to additional detection and control logic
Solution Approach 1:
The error correction mechanism is applied selectively to specific storage spaces based on their programming state. Instead of uniformly applying error correction to all storage spaces, the system identifies and applies correction only where needed (fully programmed states), reducing overall system complexity while maintaining reliability.
Solution Approach 2:
The storage space itself provides information about its state (programmed or part programmed) that the system uses to determine whether error correction is needed. This self-indicating property eliminates the need for complex external detection mechanisms.
3Productivity
If error correction mechanism is disabled for all storage spaces, then reading efficiency is improved, but data accuracy deteriorates in fully programmed states
Solution Approach 1:
The system dynamically adjusts the error correction mechanism's activation based on real-time detection of storage space states. The mechanism transitions between enabled and disabled modes, optimizing the balance between reading efficiency and data accuracy for different operational conditions.
Data Source
AI summary
This disclosure discloses a memory chip and an operating method thereof. The operating method incudes: determining whether a quantity of one or more written memory units in a storage space of the one or more storage spaces is less than or equal to a preset quantity or a write address corresponding to a write instruction is smaller than one of storage addresses of the storage space; in response to determining that the quantity of the one or more written memory units in the storage space is less than or equal to the preset quantity or the write address corresponding to the write instruction is smaller than the one of storage addresses of the storage space, determining an operating state of the storage space as a part programmed state; and disabling an error correction mechanism for the storage space in the part programmed state.