Hardware Timeout Reset for Unresponsive NAND Flash Memory
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Solution Overview
Problem
Existing semiconductor memory devices, particularly NAND flash memory, become unresponsive and lack effective methods for reset when their control circuitry and firmware controllers fail, rendering them inoperable, and adding a dedicated reset pin is costly and complex.
Innovation Solution
A hardware-based timeout circuit is implemented to detect and reset unresponsive memory devices by repurposing existing pins, such as the write protect pin, using a timeout delay to trigger a global reset without relying on internal, potentially unresponsive control circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated reset pin is added to perform reset independent of control circuitry and firmware, then the ability to reset unresponsive memory devices is improved, but the cost and complexity of the package increases
Solution Approach 1:
The write protect pin is repurposed to serve dual functions: its traditional write protection function and a new reset function. When the pin is held at a specific voltage level (e.g., ground) for a predetermined timeout period, it triggers a reset of the memory device. This eliminates the need for a dedicated reset pin while maintaining the ability to reset unresponsive devices.
Solution Approach 2:
The memory device uses its own existing pin structure and control mechanisms to perform the reset function independently. The timeout circuitry monitors the write protect pin state and automatically initiates reset after the timeout period, without requiring external control circuitry or firmware intervention.
2Device complexity
If internal control circuitry and firmware are used to process reset commands, then the reset function can be integrated, but the system becomes unresponsive when these internal components fail
Solution Approach 1:
The reset function is extracted from the internal control circuitry and firmware that can become unresponsive. By using a hardware-based timeout mechanism that monitors the write protect pin independently, the reset capability operates outside the failed internal components, ensuring reliability even when control circuitry malfunctions.
Solution Approach 2:
A hardware timeout circuit acts as an intermediary between the write protect pin and the memory array. This intermediary monitors the pin state and triggers reset independently of the main control circuitry, providing a reliable reset path that bypasses potentially failed internal components.
3Device complexity
If existing pins are repurposed for reset functionality, then the package complexity is reduced, but the original function of the pin may be compromised
Solution Approach 1:
The write protect pin is designed to perform multiple functions: traditional write protection and reset initiation. The pin can operate in write protection mode during normal operation and switch to reset mode when held at a specific voltage level for the timeout period, providing versatility without requiring additional pins.
Data Source
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AI summary
Systems and methods of memory operation that provide a hardware-based reset of an unresponsive memory device are disclosed. In one embodiment, an exemplary system may comprise a semiconductor memory device having a memory array, a controller that may include a firmware component for controlling memory operations, and a reset circuit including power-up circuitry and timeout circuitry. The reset circuit may be configured to detect when the memory device is in a non-responsive state and reset the memory device without using any internal controller components potentially impacted/affected by the non-responsive state.