Page Buffer Circuit with Dual Latches for Suspend Data Preservation

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Solution Overview

Problem

The existing semiconductor memory devices face challenges in efficiently managing the transition between normal and suspend operations, particularly in non-volatile memory devices, where data processing speed differences between volatile and non-volatile memory devices have narrowed, necessitating improved methods to suspend and resume operations without data loss.

Innovation Solution

A page buffer circuit is introduced, comprising a data latch circuit and a sensing latch circuit, which allows for data storage during normal operations and enables data transmission and sensing during suspend operations, using a static type sensing latch circuit and a dynamic type data latch circuit to facilitate seamless transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single latch circuit is used for data storage during normal operations, then the circuit structure is simple, but data loss occurs during suspend operations

Engineering Contradiction:
Improvecircuit structureVSAvoiddata preservation
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The latch circuit is divided into two separate functional units: a data latch circuit for storing data during normal operations and a sensing latch circuit for sensing and storing data during suspend operations. This segmentation allows each circuit to be optimized for its specific function, preventing data loss during operation transitions while maintaining overall system reliability.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If data is sensed and output during suspend operation, then host device access is enabled, but the normal operation cannot be resumed efficiently

Engineering Contradiction:
Improvehost device accessVSAvoidoperation resumption efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The sensing latch circuit acts as an intermediary between the memory cell array and the data latch circuit during suspend operations. It senses and stores data from the memory cells, allowing the host device to access the data while the normal operation can be efficiently resumed by transferring data back to the data latch circuit without complete operation interruption.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

Before the host device accesses data during suspend operation, the sensing latch circuit preliminarily senses and stores the data from the memory cells. This preliminary action prepares the data for output while maintaining the ability to efficiently resume normal operations by restoring data to the data latch circuit after the suspend operation completes.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If data is transferred between latch circuits during suspend operation, then data integrity is maintained, but additional circuit operations are required

Engineering Contradiction:
Improvedata integrityVSAvoidcircuit operations
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic control of data transfer between the data latch circuit and sensing latch circuit based on the operation state. During normal operations, the data latch circuit actively stores data. During suspend operations, data is dynamically transferred to the sensing latch circuit for sensing and output. After suspend operations, data is dynamically transferred back. This dynamic adaptation maintains data integrity while managing circuit operations efficiently through state-dependent data flow control.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12374406B2Page buffer circuit, method of operating a semiconductor memory device and semiconductor memory system
Publication Date: 2025.07.29 SK HYNIX INC
  • US12374406B2 patent drawing
  • US12374406B2 patent drawing
  • US12374406B2 patent drawing

AI summary

A page buffer circuit including a data latch circuit and a sensing latch circuit. The data latch circuit configured to store data corresponding to a normal operation. The sensing latch circuit configured to receive and store the data in the data latch circuit in an entering operation in accordance with a suspend operation. The sensing latch circuit configured to transmit the data stored in the sensing latch circuit to the data latch circuit in a sensing operation in accordance with the suspend operation. The sensing latch circuit configured to suspend data in a memory cell, and to output the suspend data from the memory cell.