Semiconductor Memory Structure with Segmented Word Line Connections
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Solution Overview
Problem
Existing semiconductor memory devices face issues with degraded cell current and device failure due to increased gate resistance, leading to parasitic voltage drops and read failures, particularly in advanced technologies with highly scaled dimensions.
Innovation Solution
The semiconductor memory structure incorporates a design with dedicated program and read word line connections directly over active regions and a plurality of bit lines and bit line contacts for each active region, reducing effective gate and bit line resistances.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If gate resistance is increased in advanced technology nodes, then device scaling is achieved, but parasitic voltage drop increases causing degraded word line voltage and cell current
Solution Approach 1:
The patent divides the word line connection into multiple segments: a first word line connection and a second word line connection that are separately formed and connected to the gate electrode. This segmentation allows each connection to be optimized independently, reducing the total resistance while maintaining the scaled device dimensions. The separate connections are merged at the gate electrode, effectively splitting the current path to minimize parasitic effects.
Solution Approach 2:
The patent transitions from a planar connection approach to a three-dimensional stacked connection approach. The first and second word line connections are formed in different vertical levels (different conductive layers), and they are connected to the gate electrode at different positions. This dimensional change allows the connections to be made in parallel through the vertical stack, reducing effective resistance without increasing lateral footprint, thus preserving device scaling.
2Device complexity
If conventional word line connection is used, then device structure is simple, but effective gate resistance is high causing read failures
Solution Approach 1:
The word line connection is segmented into multiple independent conductive paths (first and second connections) that converge at the gate electrode. Each segment can be formed using standard conductive layers and via structures, maintaining compatibility with existing manufacturing processes while improving electrical performance through parallel conduction paths.
Solution Approach 2:
The first and second word line connections are merged at the gate electrode, combining multiple conductive paths into a single effective connection point. This merging strategy reduces the effective gate resistance by providing multiple parallel current paths while maintaining a compact structure that does not significantly increase overall device complexity.
Data Source
AI summary
A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.