Memory Verify Control Using Source Line Discharge Transistor
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Solution Overview
Problem
The accuracy of verify operations in memory devices is compromised due to voltage fluctuations, or 'bouncing', in the source line during program loops, affecting the reliability of bit line current sensing.
Innovation Solution
A memory device with a source line discharge transistor and a control logic that adjusts the gate voltage applied to the transistor based on the number of program-completed memory cells, reducing voltage fluctuations by stepwise decreasing the gate voltage as program loops progress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a verify operation is performed on memory cells during program loops, then the threshold voltages of memory cells are verified to ensure programming accuracy, but the source line voltage fluctuates or bounces causing variation in bit line current and reducing verification accuracy
Solution Approach 1:
A source line discharge transistor is introduced as an intermediary component between the source line and ground. This transistor actively mediates the voltage fluctuations by providing a controlled discharge path for the source line, preventing voltage bouncing during verify operations and maintaining stable bit line current for accurate verification
Solution Approach 2:
The gate voltage of the source line discharge transistor is dynamically adjusted based on the number of program-completed memory cells. As programming progresses and more cells complete, the gate voltage is increased to strengthen the discharge effect and suppress voltage fluctuations more effectively, adapting the parameter response to the changing programming state
2Stability of the object's composition
If the gate voltage of the source line discharge transistor is increased to suppress voltage fluctuations, then source line voltage stability improves, but the complexity of voltage control increases
Solution Approach 1:
The control logic implements a feedback mechanism that monitors the number of program-completed memory cells and adjusts the gate voltage accordingly. This closed-loop control automatically adapts the discharge strength to the programming progress, maintaining voltage stability while simplifying the control architecture through rule-based decision making
Data Source
AI summary
Provided herein is a memory device and a method of performing a verify operation of the memory device. The memory device includes a memory cell array including memory cells, a source line discharge transistor configured to couple a source line of the memory cell array to a ground, a voltage generator configured to generate a gate voltage that is applied to a gate of the source line discharge transistor, and a control logic configured to determine the gate voltage depending on changes in threshold voltages of the memory cells in response to a verify operation on the memory cells performed in each of a plurality of program loops and to control the voltage generator to generate the determined gate voltage.