Row Decoder Bit Segmentation for Non-Power-of-Two Memory Layouts
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Solution Overview
Problem
Existing row address decoding schemes in non-volatile memory systems fail to uniquely identify each row when the number of rows in a bank is not a power of 2, or when banks contain varying numbers of sectors, leading to complex combinatorial logic requirements and increased die space.
Innovation Solution
A row address decoding scheme that uses specific bit combinations to identify banks, sectors, and rows within sectors, allowing for odd or even sector counts and non-power-of-2 row totals without additional combinatorial logic, using bit assignments that satisfy m≤2u, n≤2v, and p≤2t conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional row address decoding schemes are used, then row identification works for power-of-2 configurations, but the system becomes complex and requires more die space when handling non-power-of-2 row counts or varying sector numbers
Solution Approach 1:
The row address is segmented into multiple fields: bank field (bits [7:4]), sector field (bits [3:1]), and row field (bit [0]). This segmentation allows independent decoding of each component, enabling the system to handle non-power-of-2 configurations without complex combinatorial logic. The sector field uses a 3-to-8 decoder that can accommodate varying numbers of sectors (1-8) per bank, while the row field directly selects one of two rows within each sector.
Solution Approach 2:
Each bank is assigned a unique bank identifier in bits [7:4], allowing different banks to have different numbers of sectors (n1, n2, n3, n4) without affecting other banks. This local quality approach enables each bank to be independently configured with its own sector count, accommodating non-uniform memory architectures while using simple, identical decoder circuits in each bank.
2Adaptability or versatility
If flexible sector and row configurations are implemented, then adaptability improves, but die space increases due to additional combinatorial logic requirements
Solution Approach 1:
The address decoding is segmented into hierarchical levels: bank selection (4 bits), sector selection (3 bits), and row selection (1 bit). This segmentation eliminates the need for complex combinatorial logic that would otherwise be required to directly map arbitrary address patterns to memory locations. Each level uses simple binary decoding, significantly reducing die space while maintaining flexibility for non-power-of-2 configurations.
Solution Approach 2:
The address space is organized into multiple dimensions: bank dimension (4 banks), sector dimension (1-8 sectors per bank), and row dimension (2 rows per sector). This multi-dimensional organization allows the system to accommodate varying sector counts and non-power-of-2 total row counts without requiring complex addressing logic, as each dimension can be independently decoded with simple binary logic.
Data Source
AI summary
Numerous examples are disclosed of a row address decoding scheme. In one example, a memory system comprises m banks of non-volatile memory cells, the m banks respectively comprising n or fewer sectors and the sectors respectively comprising p rows, and a row decoder to receive a row address comprising r bits and to identify (i) a row using the least significant t bits in the r bits, (ii) a bank using the next u least significant bits, and (iii) a sector using the next v least significant bits, where m≤2u, n≤2v, and p≤2t.