Non-Volatile Memory Vertical Stacking with Guard Ring Layout
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Solution Overview
Problem
The challenge of reducing the size of non-volatile memory devices while maintaining high capacity and miniaturization is hindered by the inability to reduce the size of the peripheral circuit despite the reduction in memory cell array size.
Innovation Solution
A non-volatile memory device design featuring a first semiconductor layer with memory cells and metal lines, and a second semiconductor layer containing a page buffer circuit with first and second transistors connected to bit lines, and a guard ring overlapping the common source line tapping wire, allowing for a COP structure that reduces the size of the peripheral circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines stacked on substrate is increased to achieve high capacity, then the storage capacity is improved, but the size of memory cell array is reduced
Solution Approach 1:
The patent implements a three-dimensional vertical stacking architecture where memory cell arrays are stacked in the vertical direction above the peripheral circuit. This dimensional transition from planar to vertical arrangement allows increased storage capacity without proportionally increasing chip area, as multiple word lines are stacked vertically rather than arranged horizontally.
2Quantity of substance
If the size of memory cell array is reduced to increase capacity, then the storage density is improved, but the size of peripheral circuit cannot be reduced accordingly
Solution Approach 1:
The patent merges the peripheral circuit and memory cell array into a single integrated structure where the peripheral circuit is formed in a lower semiconductor layer and the memory cell array is stacked vertically above it. This consolidation eliminates the need for separate peripheral circuit areas, allowing the entire device footprint to be optimized for high-density storage without sacrificing circuit functionality.
Solution Approach 2:
By transitioning to a three-dimensional vertical stacking architecture, the patent allows the memory cell array to occupy the vertical space above the peripheral circuit rather than requiring additional horizontal area. This dimensional change enables high storage density while maintaining a compact overall device footprint that includes both memory and peripheral circuits.
3Length of moving object
If the chip size is reduced for miniaturization, then the device dimensions are decreased, but the peripheral circuit size reduction is insufficient
Solution Approach 1:
The patent implements vertical stacking of memory cell arrays above the peripheral circuit in the third dimension, transforming the traditional planar layout into a three-dimensional structure. This allows the chip size to be minimized in the horizontal plane while accommodating both peripheral circuits and high-capacity memory through vertical integration.
Solution Approach 2:
The patent employs a nested structure where the memory cell array is positioned vertically above and overlaps with the peripheral circuit region. This nesting arrangement allows the memory structure to be contained within the vertical projection of the peripheral circuit footprint, maximizing space utilization and minimizing overall chip dimensions.
Data Source
AI summary
A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.