Memory Block Bit-Line Layout to Reduce Source-Voltage Resistance
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Solution Overview
Problem
Existing memory devices face challenges in reducing the resistance of the path through which a source voltage is transmitted, limiting the efficiency and performance of the memory device.
Innovation Solution
The memory device incorporates a structure with dummy bit lines that are widened to facilitate the transfer of a source voltage, utilizing a double spacer patterning method to enhance the layout and reduce resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the path for source voltage transmission is made wider to reduce resistance, then the resistance is reduced, but the device area increases
Solution Approach 1:
The patent introduces dummy bit lines in addition to the normal bit lines, creating a multi-dimensional arrangement where voltage transmission paths are expanded both horizontally (through additional bit lines) and vertically (through multiple layers). This dimensional expansion allows reduced resistance without proportionally increasing the footprint area, as the dummy bit lines are integrated into the existing three-dimensional structure.
Solution Approach 2:
The patent modifies the geometric parameters of the bit lines by introducing dummy bit lines with specific width and spacing characteristics. These parameter changes create additional parallel pathways for voltage transmission, effectively reducing the overall resistance of the transmission path while maintaining compact device dimensions through optimized parameter selection.
2Reliability
If dummy bit lines are added to reduce resistance, then the voltage transmission path resistance is reduced, but the device complexity increases
Solution Approach 1:
The dummy bit lines serve multiple functions: they act as voltage transmission pathways, provide structural support for spacer formation during manufacturing, and enable optimized patterning processes. By making these elements multi-functional, the patent reduces the net increase in device complexity despite adding components to reduce resistance.
Solution Approach 2:
The dummy bit lines are positioned and structured in advance during the manufacturing process to facilitate subsequent spacer formation and patterning steps. This preliminary arrangement simplifies the overall manufacturing process by pre-establishing geometric relationships that enable automated patterning, thereby offsetting the complexity increase from adding dummy bit lines.
Data Source
AI summary
Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of memory blocks formed on a source line, the plurality of memory blocks separated by a slit, a source contact formed in the slit, a plurality of normal bit lines arranged, in parallel, over the memory blocks, the plurality of normal bit lines being spaced apart in a first direction and extending in a second direction, a plurality of dummy groups disposed between the plurality of normal bit lines, each of the plurality of dummy groups including dummy bit lines, a first dummy pad extending in the first direction and contacting end portions of the dummy groups, a first upper contact formed on the first dummy pad, and a lower contact formed between the dummy bit lines and the source contact.