Antifuse OTP Memory With Separate Paths for Stable Read Current

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Solution Overview

Problem

Existing one-time programmable (OTP) non-volatile memory technologies face performance issues due to variations in dielectric breakdown severity among antifuses, leading to inconsistent read currents and reduced device performance.

Innovation Solution

A memory device design incorporating a separate write and read path for antifuse elements, utilizing transistors to manage voltage levels and currents, ensuring consistent read currents by separating the write and read paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the program path and read path of the antifuse are the same, then the device complexity is reduced, but the read current consistency deteriorates due to dielectric breakdown severity differences

Engineering Contradiction:
Improvecircuit structure complexityVSAvoidread current consistency
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent divides the antifuse access path into two separate segments: a program path and a read path. The program path includes the antifuse element and program transistor, while the read path includes the antifuse element and read transistor. This segmentation allows independent optimization of each path, enabling consistent read currents by using a dedicated read path with controlled impedance and transistor sizing, while maintaining relatively simple overall device complexity through shared antifuse structure.

Inventive Principle:
Principle #1Segmentation

2Reliability

If separate write and read paths are implemented, then read current consistency is improved, but the device complexity increases

Engineering Contradiction:
Improveread current consistencyVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The antifuse element serves multiple functions: it can be programmed through the program path and read through the read path. The same antifuse structure is used for both programming and reading operations, but with different transistor configurations. This multi-functionality approach improves read current consistency through path separation while avoiding excessive complexity by reusing the antifuse element itself rather than creating entirely separate structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Speed

If high bias voltage is applied to program the antifuse, then the programming speed is improved, but the risk of oxide recovery increases leading to soft breakdown

Engineering Contradiction:
Improveprogramming speedVSAvoidbreakdown severity consistency
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The program transistor acts as an intermediary between the high bias voltage source and the antifuse element. It controls and regulates the current flowing through the antifuse during programming, enabling fast programming with high bias voltage while preventing excessive current that could cause oxide recovery. The transistor's channel provides a controlled path that mediates between the aggressive programming voltage and the sensitive antifuse dielectric.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Ease of operation

If the same path is used for programming and reading, then the ease of operation is improved, but the performance of memory devices deteriorates

Engineering Contradiction:
Improveoperation simplicityVSAvoidmemory device performance
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements dynamic path selection where the circuit configuration changes based on the operation mode. During programming, the program transistor is activated and the read transistor is off, directing current through the program path. During reading, the read transistor is activated and the program transistor is off, directing current through the read path. This dynamic switching maintains ease of operation through automatic path selection while achieving high performance through optimized separate paths for each operation type.

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design stabilizes read currents, reduces error rates, and minimizes the need for additional error correction circuits, enhancing the performance and reliability of OTP non-volatile memory devices.

Implementation Method 1

A high bias voltage is applied to the conducting plates making the dielectric medium broke down to program the antifuse

Methodology Applied
Scientific EffectDielectric breakdown:

Implementation Method 2

The first transistor is turned on to form a write path to the antifuse element

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 3

A third transistor is turned on to form a read path to the antifuse element

Methodology Applied
Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 4

after the dielectric medium broke down, oxide recovery occurs to the dielectric medium of some antifuses. These antifuses enter a state of soft breakdown and have smaller leakage current

Methodology Applied
Scientific EffectOxide recovery:

Data Source

PatentUS20250246253A1Memory device, integrated circuit and operating method of memory device
Publication Date: 2025.07.31 IPCELL CORPORATION LIMITED
  • US20250246253A1 patent drawing
  • US20250246253A1 patent drawing
  • US20250246253A1 patent drawing

AI summary

A memory device is provided. The memory device includes an one-time programmable non-volatile memory cell having an antifuse element, a first transistor, a second transistor and a third transistor. The antifuse element has a first terminal coupled to a program line. The first transistor is coupled between a second terminal of the antifuse element and a source line. The first transistor is turned on to form a write path to the antifuse element. A control terminal of the second transistor is coupled to a second terminal of the antifuse element. The third transistor is turned on to form a read path to the antifuse element. A first terminal of the third transistor is coupled to the source line and a second terminal of the third transistor is coupled to a first terminal of the second transistor.