Double SLC Programming for Single-Pulse NAND Sub-Block Control
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Solution Overview
Problem
Existing memory devices face increased latency in programming operations due to the need for multiple separate programming pulses and voltage ramping, particularly in high-priority and time-sensitive single level cell (SLC) programming, which affects performance in non-volatile memory devices like NAND flash.
Innovation Solution
Implementing a double single level cell (SLC) program operation where control logic applies a pass voltage to boost the channel potential of multiple sub-blocks and selectively discharges them based on a data pattern, followed by a single programming pulse to concurrently program multiple sub-blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple separate programming pulses are used to program multiple sub-blocks, then each sub-block can be programmed individually, but the latency and operation time increase
Solution Approach 1:
The patent merges multiple separate programming pulses into a single programming pulse that simultaneously programs multiple sub-blocks. The control logic applies one pulse to the wordline while selectively coupling each sub-block to the bitline based on the data pattern, achieving concurrent programming without requiring sequential pulses for each sub-block.
Solution Approach 2:
The patent introduces dynamic selective coupling between sub-blocks and bitlines during the programming operation. The control logic dynamically activates or deactivates the coupling of each sub-block to the bitline based on the data pattern, allowing flexible concurrent programming of multiple sub-blocks with a single pulse while maintaining programming accuracy.
2Manufacturing precision
If multiple separate programming operations are performed for each sub-block, then complete programming coverage is achieved, but the overall operation time increases
Solution Approach 1:
The patent combines multiple sub-block programming operations into a single unified programming operation. By selectively coupling different sub-blocks to the bitline based on the data pattern, the system achieves complete programming coverage across multiple sub-blocks while maintaining high throughput through concurrent execution.
Solution Approach 2:
The patent segments the data pattern into multiple sub-patterns, each corresponding to a different sub-block. The control logic selectively activates coupling to specific sub-blocks based on which sub-patterns require programming, enabling parallel processing of different data segments without compromising completeness.
3Reliability
If voltage ramping is performed for each programming pulse, then proper voltage levels are achieved, but the operation complexity and time increase
Solution Approach 1:
The patent merges multiple voltage ramping operations into a single voltage ramping sequence. The control logic applies one ramping operation to generate the programming voltage on the wordline, which is then dynamically distributed to multiple sub-blocks through selective coupling, eliminating the need for separate ramping operations for each sub-block.
Solution Approach 2:
The patent performs preliminary voltage ramping on the wordline before the actual programming pulse is applied. This preliminary action prepares the voltage infrastructure for concurrent programming of multiple sub-blocks, reducing the need for repeated voltage setup operations and simplifying the overall control sequence.
Data Source
AI summary
Control logic in a memory device causes a pass voltage to be applied to a plurality of wordlines of a block of a memory array of the memory device, the block comprising a plurality of sub-blocks, and the pass voltage to boost a channel potential of each of the plurality of sub-blocks to a boost voltage. The control logic further selectively discharges the boost voltage from one or more of the plurality of sub-blocks according to a data pattern representing a sequence of bits to be programmed to respective memory cells of the plurality of sub-blocks. In addition, the control logic causes a single programming pulse to be applied to a selected wordline of the plurality of wordlines of the block to program the respective memory cells of the plurality of sub-blocks according to the data pattern.