IGZO FinFET Memory Cells for Two-Bit Upper-Layer Storage
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Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in increasing the density of memory cells beyond single-bit storage capabilities.
Innovation Solution
The fabrication of multiple-time programmable (MTP) non-volatile memory (NVM) cells in upper metallization layers, utilizing FinFET transistors with dual control gates to store and access two bits of data per cell, and arranging these transistors in NAND or NOR arrays within the metallization layers to enhance device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature size is reduced to increase integration density, then more components can be integrated into a given area, but manufacturing precision and control become more difficult
Solution Approach 1:
The patent transitions from planar 2D memory structures to three-dimensional vertically-stacked FinFET structures. Multiple memory cells are stacked vertically along the channel length, utilizing the third dimension (height) to increase integration density without further reducing minimum feature sizes in the planar direction. This vertical stacking allows more memory cells to be packed into the same footprint area while maintaining manufacturable feature dimensions.
Solution Approach 2:
The patent implements nested structures where control gates are wrapped around the fin structure in a gate-all-around configuration. The FinFET channel is formed within an isolation structure, and multiple functional layers (charge trap layer, tunnel dielectric, control gates) are nested concentrically around the channel. This nesting maximizes space utilization and enables three-dimensional packing of memory cells.
2Quantity of substance
If single-bit memory cells are used, then manufacturing is simpler, but memory capacity per unit area is limited
Solution Approach 1:
The patent designs a universal FinFET memory cell structure that can store multiple bits (e.g., 2 bits or more) per physical cell through multi-level cell (MLC) or triple-level cell (TLC) operation. The same physical structure supports different storage capacities by utilizing multiple threshold states of the charge trap layer, enabling higher memory capacity without proportionally increasing device complexity. The dual control gate structure provides additional control for achieving multiple storage states.
Solution Approach 2:
The patent utilizes parameter changes in the charge trap layer to achieve multiple storage states. By controlling the amount of trapped charge within the FinFET channel, the device can exhibit multiple threshold voltage states (e.g., 0, 1, 2, 3 bits), allowing a single physical memory cell to store multiple bits of information. This parameter-based encoding increases memory capacity without requiring additional physical cells.
3Quantity of substance
If vertically-stacked FinFET structures are implemented, then three-dimensional integration is achieved, but fabrication process complexity increases
Solution Approach 1:
The patent divides the memory device into modular repeating units - individual FinFET memory cells stacked vertically. Each FinFET cell is a self-contained module with its own channel, isolation structure, and control gates. This segmentation allows the complex three-dimensional structure to be built through repeated application of standardized fabrication steps, reducing overall process complexity compared to creating entirely unique three-dimensional structures.
Solution Approach 2:
The patent employs preliminary actions in the fabrication sequence, such as forming the isolation structure and charge trap layer before creating the FinFET channel, and establishing the vertical stacking geometry early in the process. By preparing the three-dimensional framework in advance, subsequent steps can focus on adding functional layers rather than creating the complex geometry from scratch, simplifying the overall fabrication process.
Data Source
AI summary
A semiconductor fabrication method includes providing a substrate with a logic device formed on the substrate and a plurality of metal routing layers disposed above the logic device and substrate with metal routing connected to the logic device, the plurality of metal routing layers including an upper metal routing layer with metal lines, vias, and a planarized oxide layer; forming a fin structure over the oxide layer in the upper metal routing layer from IGZO; forming a high-K dielectric layer over the oxide layer and the fin structure; forming a storage gate over channel regions of the fin structure; forming a first control gate on a first side of the storage gate; forming a second control gate on a second side of the storage gate; and connecting the first control gate to a first word line and the second control gate to a second word line.