Multi-Level Memory Storage Using Series-Parallel Resistance Sensing

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Solution Overview

Problem

Existing memory devices struggle to efficiently store multi-level data while maintaining area efficiency, as volatile memory devices lose data when power is off and non-volatile memory devices are slower.

Innovation Solution

A memory system with a plurality of memory cells connected in series and parallel configurations, controlled by a memory controller to program and read multi-level data based on resistance changes, allowing each cell to represent multiple states efficiently.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If volatile memory devices are used to store data, then data access speed is improved, but data retention is worsened (data is lost when power is off)

Engineering Contradiction:
Improvedata access speedVSAvoiddata retention
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent combines volatile and non-volatile memory characteristics into a single memory device structure. The memory device includes a storage unit that can retain data without power (non-volatile characteristic) and a readout mechanism that enables fast data retrieval (volatile characteristic). This merging resolves the contradiction by achieving both data retention and fast access speed in one device.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If non-volatile memory devices are used to store data, then data retention is improved, but data access speed is worsened

Engineering Contradiction:
Improvedata retentionVSAvoiddata access speed
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent implements a charge pump circuit that pre-charges capacitors during a programming operation. This preliminary action stores energy in the capacitors, which is then used to rapidly discharge and readout data when needed. The preliminary charging of capacitors enables fast data access while maintaining non-volatile storage, resolving the speed-retention contradiction.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If multi-level data storage is implemented, then storage density is improved, but device complexity is worsened

Engineering Contradiction:
Improvestorage densityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent uses parameter changes in the readout mechanism to distinguish between different data states. By varying the readout signal parameters (voltage levels, current thresholds), the system can differentiate between multiple stored states (e.g., 0, 1, 2, 3) without requiring separate physical structures for each state. This approach increases storage density while managing device complexity through software/firmware-based state differentiation.

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The system achieves area-efficient storage and reading of multi-level data by utilizing the resistance changes in series and parallel connections of memory cells, enabling efficient storage and retrieval of multiple bits with a single current measurement.

Implementation Method 1

program and read multi-level data based on resistance changes

Methodology Applied
Scientific EffectResistive switching: Electrical Resistance

Data Source

PatentUS12380947B2Systems and methods to store multi-level data
Publication Date: 2025.08.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12380947B2 patent drawing
  • US12380947B2 patent drawing
  • US12380947B2 patent drawing

AI summary

Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.