Memory Device Page Buffer Two-Stage Charging for 3D Peak Current Control
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Solution Overview
Problem
The increase in memory integration level in three-dimensional memories leads to higher instantaneous peak currents, affecting normal operation.
Innovation Solution
A two-stage charging method is implemented, where the first sensing node is charged to a first voltage through a first charge circuit and then the first sensing node and the bit line are charged to a higher second voltage through a second charge circuit, dividing the peak current into smaller currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory integration level is increased in three-dimensional memories, then memory capacity and density are improved, but instantaneous peak current increases and affects normal operation
Solution Approach 1:
The charging operation is segmented into two distinct stages: a first charge stage that charges the first sensing node to a first voltage, and a second charge stage that charges the first sensing node and bit line to a second voltage. This segmentation divides the peak current into two smaller peak currents, resolving the contradiction between high memory integration and peak current management
2Quantity of substance
If memory integration level is increased, then memory capacity is improved, but voltage fluctuations increase and affect normal operation
Solution Approach 1:
The voltage charging process is segmented into two stages with different target voltages. The first stage charges to a first voltage, and the second stage charges to a second voltage. This segmentation reduces voltage fluctuations by controlling the charging process in controlled increments, allowing high memory integration while maintaining voltage stability
Solution Approach 2:
The first charge stage performs a preliminary charging action to bring the sensing node to an intermediate voltage state before the second charge stage completes the charging to the final voltage. This preliminary action prepares the circuit for the subsequent charging phase, reducing overall voltage fluctuations
Data Source
AI summary
The present disclosure provides a memory device and an operation method thereof, and a memory system, wherein the memory device includes a memory array and a page buffer circuit coupled with a bit line in the memory array; the page buffer circuit includes a first charge circuit and a second charge circuit coupled to a first sensing node along with the first charge circuit; and the operation method of the memory device includes: in a first charge stage, charging the first sensing node to a first voltage through the first charge circuit; and in a second charge stage, charging the first sensing node and the bit line to a second voltage through the second charge circuit, wherein the second voltage is higher than the first voltage.