Flash Memory Read Retry Table Grouping for Faster Decoding

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Solution Overview

Problem

Existing flash memory controllers face performance degradation due to high bit error rates and frequent adjustments of read retry tables, leading to decoding failures and reduced processing speed, especially when bit error counts exceed a threshold.

Innovation Solution

Classify read retry tables into groups based on decoding success and syndrome weights, prioritizing tables with higher decoding success rates to quickly find suitable reading voltages, reducing the need for sequential retries.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the flash memory controller uses multiple read retry tables to read the flash memory module, then the decoding success rate can be improved, but the processing speed is significantly reduced when bit error count exceeds threshold

Engineering Contradiction:
Improvedecoding success rateVSAvoidprocessing speed
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent divides the multiple read retry tables into different groups (first group with higher decoding success rate, second group with lower decoding success rate) based on their performance characteristics. This segmentation allows the controller to selectively use appropriate tables rather than sequentially trying all tables, thereby improving both decoding success rate and processing speed.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different strategies to different groups of read retry tables. The first group of tables (with higher decoding success rate) is used preferentially when bit error count is within threshold, while the second group is used when bit error count exceeds threshold. This local differentiation optimizes both reliability and productivity by matching the right table to the right error condition.

Inventive Principle:
Principle #3Local quality

2Adaptability or versatility

If the flash memory controller sequentially selects multiple read retry tables, then more reading voltages can be tried, but the system performance is degraded due to frequent adjustments and decoding failures

Engineering Contradiction:
Improvereading voltage optionsVSAvoidsystem performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent pre-classifies and sorts read retry tables into groups based on their decoding success rates before actual reading operations. This preliminary organization allows the controller to quickly select appropriate tables without sequentially trying all options, thereby maintaining adaptability while improving system performance by reducing frequent adjustments.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the flash memory controller uses read retry tables with higher decoding success rate, then fewer retry attempts are needed, but the versatility of reading voltages is reduced

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidreading voltage diversity
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent creates a dynamic selection mechanism where the controller adapts its reading voltage choices based on real-time error conditions. When bit error count is within threshold, the controller uses tables from the first group (higher decoding success rate). When bit error count exceeds threshold, the controller switches to tables from the second group (lower decoding success rate but more voltage diversity). This dynamic adaptation maintains both decoding efficiency and versatility.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS12373284B2Method for accessing flash memory module and associated flash memory controller and electronic device
Publication Date: 2025.07.29 SILICON MOTION INC
  • US12373284B2 patent drawing
  • US12373284B2 patent drawing
  • US12373284B2 patent drawing

AI summary

The invention provides a method for accessing a flash memory module, wherein the method includes the steps of: classifying multiple read retry tables into at least a first group and a second group to establish a classifying and sorting table, wherein each of the multiple read retry tables records at least one reading voltage, and any two read retry tables do not have exactly the same reading voltage; selecting a first read retry table from the first group to read a page of a block of the flash memory module to generate first read data; and when a decoder fails to decode the first read data, selecting a second read retry table from the first group to read the page of the block of the flash memory module to generate second read data for the decoder to decode.