NAND Flash Pass Voltage Control for Reduced Pass Disturb
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Solution Overview
Problem
NAND flash memory devices experience retention and disturb phenomena due to electron leakage in floating gates when excessive pass voltages are applied, affecting data retention and integrity.
Innovation Solution
A memory device with a pass voltage information generator that monitors the voltage level of a common source line and determines the appropriate pass voltage based on clock counts, using a mapping table to adjust the pass voltage accordingly to prevent excessive voltage application.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high pass voltage is applied to unselected word lines, then read operation speed is improved, but electron leakage occurs causing disturb phenomena
Solution Approach 1:
The patent applies dynamics by making the pass voltage adjustable rather than fixed. The pass voltage determiner dynamically selects the pass voltage level based on the number of clocks counted during the read operation, allowing the system to adapt the voltage to different operational conditions and memory states, thereby resolving the contradiction between speed and reliability
Solution Approach 2:
The patent changes the voltage parameter dynamically based on operational conditions. By counting clocks to determine operation duration or state, and then selecting appropriate pass voltage levels from multiple available levels, the system optimizes the voltage parameter to prevent electron leakage while maintaining read speed performance
2Measurement precision
If an excessive pass voltage is applied to unselected word lines, then read margin is improved, but retention phenomenon occurs due to electron leakage
Solution Approach 1:
The patent implements feedback by using the clock count information (which reflects the state of the memory system) to determine the appropriate pass voltage. This feedback mechanism allows the system to adjust the pass voltage based on actual operational conditions, preventing excessive voltage application that would cause retention phenomena while maintaining adequate read margin
Solution Approach 2:
The system dynamically adjusts the pass voltage level based on real-time clock counting feedback, transitioning from a static voltage application approach to a dynamic one that responds to system state, thereby preventing harmful retention phenomena while maintaining read performance
Data Source
AI summary
A memory device includes: a memory cell array including a cell string including a plurality of memory cells respectively connected between a common source line and a plurality of bit lines; a peripheral circuit for performing an internal operation on the memory cells; and control logic for controlling the peripheral circuit to apply a voltage necessary for the internal operation to word lines connected to the plurality of memory cells. The peripheral circuit includes a pass voltage information generator for generating pass voltage information including a number of clocks input from a time at which a pass voltage is applied to the word lines to a time at which a voltage level of the common source line reaches a predetermined reference level. The control logic includes a pass voltage determiner for determining a pass voltage to be applied to the word lines, based on the pass voltage information.