Vertical Channel Memory Structure for Faster Read Stabilization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Vertical memory devices with channel holes experience variations in memory cell characteristics due to distance from channel holes to isolation regions, leading to increased operation time.
Innovation Solution
Applying a negative bias voltage to unselected string selection lines after a prepulse voltage in memory devices with vertical channel structures, and adjusting voltage levels based on the distance to adjacent word line cut regions to optimize read operation efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertical channel structures are used in memory devices, then memory capacity and integration density are improved, but operation time increases due to characteristic variations in memory cells at different distances from isolation regions
Solution Approach 1:
A prepulse voltage is applied to unselected string selection lines before the actual read operation to pre-condition the vertical channel structures. This preliminary action equalizes the electrical characteristics of memory cells at different positions, reducing variation effects and enabling faster subsequent operations.
Solution Approach 2:
Different voltage levels are applied to string selection lines based on their distance from word line cut regions. Memory cells closer to isolation regions receive different voltage conditioning than those farther away, compensating for the characteristic variations and reducing overall operation time.
2Stability of the object's composition
If different voltage levels are applied to string selection lines based on distance to word line cut regions, then memory cell characteristic uniformity is improved, but device complexity increases
Solution Approach 1:
The memory device divides string selection lines into multiple groups based on their distance from word line cut regions. Each group receives appropriately tailored voltage levels, allowing uniform memory cell characteristics while managing complexity through systematic segmentation rather than individual customization.
3Speed
If prepulse voltage is applied to unselected string selection lines, then bit line level stabilization time is reduced, but energy consumption increases
Solution Approach 1:
The prepulse voltage is applied only to unselected string selection lines and only for the duration necessary to stabilize bit line levels, rather than continuously or to all lines. This partial application of voltage achieves the required stabilization speed while minimizing unnecessary energy consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Reduces prepulse operation time and enhances the reliability of memory cell operations by stabilizing bit line levels quickly, thereby improving the overall performance of vertical memory devices.
Implementation Method 1
a negative charge pump configured to generate a bias voltage of a negative level to be applied to at least one of the plurality of string selection lines
Data Source
AI summary
Provided is a memory device with a vertical channel structure. The memory device includes a memory cell array including a plurality of memory cells and a plurality of string selection lines, a negative charge pump configured to generate a bias voltage of a negative level, to be applied to at least one of the plurality of string selection lines, and a control logic circuit configured to apply, for a first period, a prepulse voltage to at least one unselected string selection line among the plurality of string selection lines excluding a selected string selection line to which a memory cell selected from among the plurality of memory cells is connected and thereafter apply the bias voltage to the at least one unselected string selection line so as to perform a read operation on the selected memory cell.