Memory Cell Block Layout for Ground Select Line Isolation
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Solution Overview
Problem
The increase in integration density of memory devices leads to interference among word lines, string select lines, and ground select lines, degrading the reliability of data storage.
Innovation Solution
A memory device with a memory cell array comprising a first cell block storing non-user data and a second cell block storing user data, where ground select transistors in the first cell block are programmed to different threshold voltages, and a first line is arranged at the same height as a word line in the second cell block to enhance electrical separation and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration density of memory devices is increased, then the capacity and integration density of memory devices are improved, but the interference among word lines, string select lines, and ground select lines increases, degrading data reliability
Solution Approach 1:
The memory device is divided into multiple cell blocks (first cell block for non-user data, second cell block for user data), with each block having differentiated ground select transistor configurations. This segmentation allows optimized control of interference in different regions while maintaining high integration density.
Solution Approach 2:
Ground select transistors in the first cell block are programmed to different threshold voltages (first threshold voltage for transistors connected to GSLs, second threshold voltage higher than the first for transistors not connected to GSLs). This local differentiation of transistor properties enables reduced interference in critical areas while maintaining overall integration density.
2Reliability
If ground select transistors are programmed to different threshold voltages, then the reliability of data is improved by reducing interference, but the device complexity increases
Solution Approach 1:
Different threshold voltages are assigned to ground select transistors based on their specific locations and connections within the cell block. Transistors connected to GSLs receive the first threshold voltage, while those not connected to GSLs receive the second threshold voltage. This localized differentiation improves reliability without requiring complete redesign of the entire transistor array.
Solution Approach 2:
The threshold voltages of ground select transistors are programmed during the manufacturing process before the memory device is put into service. This preliminary programming ensures that the interference reduction mechanism is already in place, eliminating the need for complex runtime adjustments or reconfiguration.
Data Source
AI summary
A memory device comprises: a memory cell array including a plurality of cell blocks including a first cell block storing information other than user data and a second cell block storing the user data, wherein each of the plurality of cell blocks includes a plurality of cell strings and control circuitry configured to control a write operation and a read operation of the memory cell array. A first ground select line (GSL) region included in the first cell block includes a plurality of GSLs stacked in a vertical direction. One or more ground select transistors of a plurality of ground select transistors connected to each of the GSLs are programmed to a first threshold voltage and the other ground select transistors of the plurality of ground select transistors not connected to the GSLs are programmed to a second threshold voltage that is higher than the first threshold voltage. A first line included in the first GSL region in the first cell block is arranged at a same height as a word line connected to memory cells storing the user data in the second cell block.