NAND Read Operations with Pattern-Based Reference Voltage Adaptation
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Solution Overview
Problem
Existing memory technologies face issues with erroneous readings due to shifting stored voltages in multi-bit memory cells, leading to increased processing time and overhead lag during read operations, as conventional methods like CRC and ARC require multiple retries to recalibrate reference drive voltages.
Innovation Solution
Dynamically select reference drive voltages based on sensed patterns in the output of memory cells during the read process, using multiple reference drive voltages to detect and modify patterns before final read operations, reducing the need for extensive retries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional methods (CRC, ARC) are used to detect and correct erroneous readings, then reading reliability is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by detecting patterns in intermediate data output during the read process itself, before the final read operation completes. By monitoring voltage levels at multiple reference points during the read sequence, the system can identify shifting patterns early and adjust reference voltages proactively, eliminating the need for post-error detection and retry cycles that consume additional time.
Solution Approach 2:
The patent implements feedback by continuously monitoring the output voltage levels during the read process and using this information to dynamically adjust reference voltages. The system compares actual voltage levels against expected ranges and modifies subsequent read operations based on detected patterns, creating a closed-loop system that adapts to voltage shifts in real-time without requiring separate error detection and correction phases.
2Measurement precision
If multiple reference drive voltages are used to read multi-bit cells, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies dynamics by making the reference voltage selection adaptive rather than fixed. The system dynamically adjusts which reference voltages to apply based on detected patterns in the data output, allowing the same hardware to handle different storage conditions automatically. This eliminates the need for complex manual calibration procedures while maintaining high precision across varying voltage levels.
Solution Approach 2:
The patent changes the parameter of reference voltage selection based on detected patterns in the data. By monitoring voltage levels and identifying shifts, the system modifies the reference voltage parameters dynamically during operation. This allows the system to maintain measurement precision across different storage states without requiring a completely different hardware architecture for each voltage level.
3Reliability
If read retry voltages are used after detecting erroneous reads, then reading reliability is improved, but overhead lag time increases
Solution Approach 1:
The patent applies preliminary action by detecting voltage shift patterns during the initial read operation itself, before any errors occur. By monitoring intermediate data output and identifying trends in voltage levels, the system can proactively adjust reference voltages to prevent erroneous reads, eliminating the need for subsequent retry operations and their associated delays.
Solution Approach 2:
The patent skips the traditional error detection and retry cycle by implementing continuous pattern detection during the read process. Instead of completing a full read operation, detecting errors, then retrying with new voltages, the system rushes through the process by simultaneously performing voltage level monitoring and reference voltage adjustment in parallel, significantly reducing overhead lag time.
Data Source
AI summary
A method comprises applying a first reference drive voltage to a wordline of memory cells to generate a respective first resulting voltage level from each respective cell in the wordline, and storing in memory a first respective logic value indicated by the respective first resulting voltage level for each memory cell. The method further comprises applying a second reference drive voltage to the wordline of memory cells to generate a respective second resulting voltage level from each respective cell in the wordline while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by the respective second resulting voltage level, and at least one of the first reference drive voltage and the second reference drive voltage is modified based on the detected pattern data.