Memory Wordline Switch Scaling with Zone-Based Negative Bitline Bias
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Solution Overview
Problem
Conventional memory devices face inefficiencies in programming word lines due to increasing width of word line switch transistors, leading to challenges in scaling and programming efficiency.
Innovation Solution
The memory device groups word lines into zones based on the size of the associated word line switch transistors, and adjusts the negative biasing voltage on the bitline during programming based on the zone, using a bitline biasing circuit to optimize programming loops.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the word line switch transistor size is increased to accommodate more word lines, then the memory device can support more memory cells, but the programming efficiency deteriorates and scaling becomes challenging
Solution Approach 1:
The patent divides the bitline into multiple segments by introducing intermediate bitline nodes between different groups of memory cells. This segmentation allows independent voltage control for different word line groups, enabling efficient programming of multiple word lines simultaneously without requiring excessive current through a single large transistor, thus maintaining programming efficiency while supporting increased memory capacity
Solution Approach 2:
The patent introduces a new voltage dimension by applying negative voltages to intermediate bitline nodes during programming operations. This additional voltage dimension enables better control over the programming process for different word line groups, allowing efficient programming of scaled-up memory arrays without proportionally increasing transistor size
2Adaptability or versatility
If the word line switch transistor size is increased to drive more word lines, then more memory cells can be accessed, but the device area and complexity increase
Solution Approach 1:
The bitline is segmented into multiple sections with intermediate nodes that can be independently controlled. This segmentation allows the use of smaller, more manageable transistors for each word line group while collectively accessing a larger number of word lines, reducing both individual transistor size and overall device complexity
Solution Approach 2:
The intermediate bitline nodes serve multiple functions: they act as voltage control points for different word line groups, serve as current distribution nodes, and enable independent programming of multiple word lines. This multi-functionality reduces the need for dedicated large transistors for each word line, simplifying the overall device structure
Data Source
AI summary
A memory device is provided and includes a memory block that has a plurality of memory cells that are arranged in a plurality of word lines. The memory device also includes a plurality of word line switch transistors that are electrically coupled with the plurality of word lines, where the plurality of word lines are grouped into a plurality of zones based on a size of a word line switch transistor associated with each word line of the plurality of word lines. The memory device also includes a bitline biasing circuit for providing a negative biasing voltage to a bitline corresponding to a memory cell of the selected word line during programming of the selected word line and the bitline biasing circuit is configured to set a magnitude of the negative biasing voltage based on which zone of the plurality of zones the selected word line is in.