Non-Volatile Memory Bias Ramps for Faster Post-Erase Defect Testing
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Solution Overview
Problem
Existing non-volatile memory testing for defects during the erase operation is time-consuming, which degrades memory performance, and there is a need for faster defect testing to maintain high operational speeds.
Innovation Solution
Incorporating faster ramp rates for bias levels during post-erase tests in non-volatile memory arrays, specifically for word lines, to reduce the time penalty associated with standard read, program verify, or read verify operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If standard read, program verify, or read verify operations are performed during post-erase tests, then measurement precision is improved, but time consumption increases
Solution Approach 1:
The patent changes the ramp rate parameter for bias levels during post-erase tests. By using faster ramp rates for word line bias levels while maintaining standard ramp rates for other signals, the testing time is reduced without compromising defect detection accuracy. This selective parameter modification resolves the contradiction between fast testing and precise measurement.
2Productivity
If faster ramp rates are used for bias levels during post-erase tests, then productivity is improved, but measurement precision may deteriorate
Solution Approach 1:
The patent applies different ramp rates to different signals during post-erase tests. Specifically, faster ramp rates are applied only to word line bias levels, while other signals maintain standard ramp rates. This localized differentiation allows speed improvement in critical paths without compromising overall measurement precision, resolving the contradiction between productivity and measurement quality.
Data Source
AI summary
As part of the erase operation for a memory block, one or more post-erase tests can be incorporated into the erase operation to see whether the block has grown any defects. After erasing a block and verifying the erase, the post-erase tests can be performed on the block. As these test involve biasing the block and performing a sensing operation, these post erase tests come with a time penalty. To reduce the associated time penalty and improve memory performance while incorporating the defect tests into the erase process, when biasing the memory array for the post-erase defect tests different ramp rates can be used. In particular, faster ramp rates for bias levels, such those applied to the word lines of the block, are used for the post-erase tests than are used for the same bias level when performing the standard read, program verify, or read verify operations.