Interface Charge-Trap Memory for Low-Voltage OTP Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing one-time programmable (OTP) memory devices require high programming voltages and have large sizes due to anti-fuse structures, which are inefficient and cumbersome.
Innovation Solution
Incorporating charge traps along the interface between a ferroelectric layer and a channel layer, allowing for low-voltage programming (≤2 volts) and reduced device size by trapping charge carriers to shift the threshold voltage, utilizing materials like tungsten, hafnium zirconium oxide, and indium gallium zinc oxide.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If anti-fuse structures are used for one-time programmable memory, then permanent data storage is achieved, but programming voltage requirement increases and device size increases
Solution Approach 1:
The patent changes the physical mechanism from anti-fuse breakdown (high voltage) to ferroelectric polarization switching (low voltage). By utilizing the ferroelectric effect and interface charge traps, the programming operation switches from a high-voltage destructive process to a low-voltage reversible polarization process, reducing programming voltage from typically >10V to <2V while maintaining permanent storage capability through stable polarization states.
Solution Approach 2:
The patent employs composite material structures including ferroelectric layers (e.g., hafnium zirconium oxide), channel layers (e.g., indium gallium zinc oxide), and gate electrodes. This composite approach combines the non-volatile storage capability of ferroelectric materials with the charge trapping mechanism at interfaces, achieving both permanent storage and low-voltage operation that neither material alone could provide.
2Reliability
If anti-fuse structures are used for one-time programmable memory, then permanent data storage is achieved, but device size increases
Solution Approach 1:
The patent extracts the data storage function from the bulky anti-fuse structure and implements it through ferroelectric polarization states in a thin-film stack. By removing the anti-fuse component and using the ferroelectric layer's polarization orientation (upward or downward) to represent binary states, the device achieves permanent storage in a much more compact form factor suitable for modern high-density memory applications.
Solution Approach 2:
The patent transitions from planar anti-fuse structures to vertically stacked ferroelectric memory cells with multiple layers (gate, ferroelectric, channel, electrode). This vertical stacking in the third dimension enables higher storage density and smaller device footprint while maintaining the one-time programmable functionality through stable polarization states.
3Device complexity
If conventional memory structures are used, then device simplicity is maintained, but programming speed and current increase
Solution Approach 1:
The patent exploits the ferroelectric phase transition and polarization switching mechanism to achieve rapid programming. The ferroelectric material can switch between opposite polarization states extremely quickly (nanosecond to picosecond scale) under low voltage, enabling fast programming speeds while maintaining a relatively simple device structure that resembles conventional FET-based memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution reduces programming voltage requirements and device size while maintaining permanent data storage, enhancing performance by increasing current and speed through the memory device.
Implementation Method 1
A ferroelectric layer is directly between the channel layer and the gate layer
Implementation Method 2
A plurality of charge traps are along an interface between the ferroelectric layer and the channel layer
Data Source
AI summary
An integrated chip including a substrate. A gate layer is over the substrate. A channel layer is over the substrate and vertically spaced apart from the gate layer. A ferroelectric layer is directly between the channel layer and the gate layer. A pair of source/drain electrodes are laterally spaced apart over the channel layer. A plurality of charge traps are along an interface between the ferroelectric layer and the channel layer.