Memory Array Pulse Sequencing to Reduce Program Crosstalk
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Solution Overview
Problem
The existing semiconductor memory technologies face issues with program crosstalk due to electrical leakage in unselected memory strings, primarily caused by voltage spikes in top select gate lines during programming operations.
Innovation Solution
The proposed solution involves applying a first pulse to a word line to reach a target voltage at a first time instant and a second pulse to an adjacent top select gate line to reach a second target voltage at a later time instant, thereby reducing the voltage spike and minimizing electrical leakage in unselected memory strings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a voltage pulse is applied to the word line to reach target voltage at a first time instant, then the programming operation can be performed, but a voltage spike occurs in the adjacent top select gate line causing electrical leakage in unselected memory strings
Solution Approach 1:
The patent applies a preliminary action by enabling the top select transistor before applying the word line voltage pulse. The control signal is applied to the top select gate line before the word line pulse, ensuring the transistor is in the on-state beforehand. This prevents the voltage spike from causing harmful electrical leakage while maintaining programming operation speed.
Solution Approach 2:
The patent implements preliminary anti-action by applying a control signal to the top select gate line before the word line voltage pulse is applied. This anticipatory control prevents the voltage spike from causing electrical leakage in unselected memory strings by ensuring the transistor is already in the appropriate state, thereby counteracting the potential harmful effect before it occurs.
2Reliability
If the top select transistor is enabled before word line voltage pulse, then electrical leakage is reduced, but the timing control complexity increases
Solution Approach 1:
The patent uses preliminary action by applying the top select gate control signal before the word line voltage pulse. This timing sequence ensures the transistor is enabled in advance, preventing electrical leakage while using a simple sequential control approach that does not significantly increase overall timing control complexity.
Solution Approach 2:
The patent employs periodic action through the sequential application of control signals - first enabling the top select transistor, then applying the word line voltage pulse. This periodic timing sequence simplifies the control logic by using clear sequential steps rather than complex simultaneous control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces the probability of electrical leakage in unselected memory strings, thereby improving the program crosstalk problem by controlling the timing and duration of voltage application in the memory cells.
Implementation Method 1
due to a coupling effect of the voltage of the first word line, a voltage spike may occur in the first top select gate line
Data Source
AI summary
A memory, an operation method thereof, and a memory system are provided. The memory includes: a memory cell array including memory strings each including memory cells and top select transistors; top select gate lines coupled to top select transistors; word lines coupled to memory cells; and a peripheral circuit coupled to top select gate lines and word lines and configured to: apply a first pulse to a first word line of word lines, such that a voltage of the first word line reaches a first target voltage at a first time instant; apply a second pulse to a first top select gate line of top select gate lines adjacent to the first word line, such that a voltage of the first top select gate line reaches a second target voltage at a second time instant that is later than the first time instant.