Differential Memory Cell Array for Selective Cell Erase
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Solution Overview
Problem
Conventional non-volatile memory cell arrays lack the ability to perform erase operations on individual memory cells, requiring the erasure of all memory cells in a segment or area, limiting data management flexibility.
Innovation Solution
A differential memory cell array structure is introduced, comprising select transistors, floating gate transistors, coupling devices, and capacitors, allowing for independent erase operations on each memory cell through controlled bias voltages and Fowler-Nordheim electron tunneling effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional memory cell array structure is used, then erase operation can be performed on segments or areas, but individual memory cell erase capability is lost
Solution Approach 1:
The memory cell array is divided into multiple independently controllable memory cells, each with its own select transistors. This segmentation allows individual cells to be selected and erased independently while maintaining the overall array structure, resolving the contradiction between erase flexibility and structural complexity.
Solution Approach 2:
Different regions of the memory cell array are given different select transistor control capabilities. Specifically, first select transistors control first memory cells while second select transistors control second memory cells, allowing localized erase operations on individual cells or groups of cells without affecting other regions, thus achieving both flexibility and manageable complexity.
2Ease of operation
If segment erase operation is performed on conventional memory, then all memory cells in the segment are erased, but selective erase of individual cells is impossible
Solution Approach 1:
The select transistor control is made dynamic and configurable. First select transistors can be independently controlled from second select transistors, allowing the system to adaptively select which memory cells to erase based on operational requirements. This dynamic control enables precise data management without unintended data loss while maintaining ease of operation.
Solution Approach 2:
The dual select transistor architecture provides feedback control mechanisms where the state of first and second memory cells can be independently monitored and controlled. This allows selective erase operations to be performed only on intended target cells while preserving data in other cells, resolving the contradiction between operational ease and information loss prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables selective programming, reading, and erasing of individual memory cells within the array, enhancing data management capabilities and preventing unintended data loss in unselected cells.
Implementation Method 1
A first terminal of the first capacitor is connected to a floating gate of the first floating gate transistor
Implementation Method 2
allowing for independent erase operations on each memory cell through controlled bias voltages and Fowler-Nordheim electron tunneling effects
Data Source
AI summary
A differential memory cell array structure for a MTP non-volatile memory is provided. The array structure is connected to a source line, a word line, a bit line, an inverted bit liner and an erase line. After an erase operation (ERS) is completed, the stored data in the differential memory cells of the selected row are not all erased. That is, only the stored data in a single selected memory cell of the selected row is erased.