Memory Pass-Transistor Circuit Layout for Word-Line Loading Balance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing number of word lines and pass transistors in memory devices due to high integration density leads to increased chip size and loading time skew, complicating the wiring structures and overall design.
Innovation Solution
A memory device design with a pass transistor circuit that includes an odd number of pass transistor groups, where transistors connected to word lines at the same level are adjacently disposed, reducing wiring resistance variations and loading time skew, and incorporating a COP structure to maintain chip size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of word lines and pass transistors is increased to achieve high integration density, then storage capacity is improved, but chip size increases and wiring structures become complex
Solution Approach 1:
The patent transitions from a planar arrangement of memory blocks to a three-dimensional stacked configuration where memory blocks are vertically arranged. This vertical stacking enables high integration density without increasing the lateral chip footprint, effectively resolving the contradiction between storage capacity and chip size.
Solution Approach 2:
The patent merges multiple memory blocks into a single stacked structure with shared peripheral circuits. By combining the functionality of multiple blocks and using common pass transistor circuits for vertical word lines, the design achieves high capacity while minimizing the area occupied by redundant circuitry.
2Quantity of substance
If more pass transistors are connected to vertically stacked word lines to increase integration density, then storage capacity is improved, but loading time skew increases
Solution Approach 1:
The pass transistor circuit is segmented into multiple groups, with each group handling specific word lines. This segmentation allows for organized signal distribution and reduces the complexity of timing coordination across all transistors, thereby minimizing loading time skew while maintaining high integration density.
Solution Approach 2:
The patent introduces a vertical dimension to the word line architecture, with word lines stacked perpendicular to the substrate. This vertical stacking, combined with grouped pass transistors, creates a structured approach to signal distribution that reduces timing variations compared to traditional planar expansions.
3Quantity of substance
If the number of memory blocks is increased to achieve high integration density, then storage capacity is improved, but wiring structures become complex
Solution Approach 1:
The patent implements universal peripheral circuits that serve multiple memory blocks simultaneously. The pass transistor circuits and control logic are designed to handle vertically stacked word lines from multiple blocks through a unified interface, eliminating the need for separate wiring structures for each block and significantly reducing overall wiring complexity.
Data Source
AI summary
A memory device includes: a memory cell array including a first memory block and a second memory block adjacently disposed in a first direction, driving signal lines respectively corresponding to vertically stacked word lines, and a pass transistor circuit including an odd number of pass transistor groups and connected between the driving signal lines and the memory cell array. One of the odd number of pass transistor groups includes a first pass transistor connected between a first word line of the first memory block and a first driving signal line among the driving signal lines, and a second pass transistor connected between a first word line of the second memory block and the first driving signal line adjacently disposed to the first pass transistor in a second direction.