X-Direction Divided NAND Sub-Blocks for Selective Parallel Operations
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Solution Overview
Problem
Existing memory systems face challenges in efficiently performing parallel memory operations in three-dimensional NAND structures due to the limitations of area trade-offs between memory structures and peripheral circuitry, as well as differing processing technologies, which affect scalability and performance.
Innovation Solution
The memory system is divided into x-direction sub-blocks, allowing parallel memory operations in multiple XY sub-blocks while inhibiting operations in others, with each sub-block connected to a different set of bit lines, and separating memory structure and peripheral circuitry onto separate dies for optimized fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory operations are performed in parallel across the entire block, then productivity is improved, but it becomes difficult to inhibit operations in specific regions
Solution Approach 1:
The block is divided into multiple sub-blocks along the x-direction, with each sub-block independently controllable through separate word line sets (WL0-WL7 for first sub-block, WL8-WL15 for second sub-block). This segmentation enables selective inhibition of specific sub-blocks while maintaining parallel operations in others, resolving the contradiction between productivity and selective control.
2Device complexity
If memory structure and peripheral circuitry are integrated on the same die, then device complexity is reduced, but scalability and performance optimization are limited
Solution Approach 1:
The patent separates the memory structure (NAND strings) from the peripheral circuitry (control circuits) onto different dies. The memory structure die contains the memory cells and bit lines, while the peripheral circuitry die contains the control logic. This extraction enables independent optimization of each component for its specific fabrication requirements, improving scalability and performance while managing device complexity through modular architecture.
Data Source
AI summary
A memory system having an x-direction (bit line direction) divided sub-block mode. Each block is divided in a y-direction and in the x-direction into a number of groups of contiguous NAND strings that are referred to as XY sub-blocks. The memory system performs a memory operation in parallel in multiple XY sub-blocks in a block while inhibiting the memory operation in the other XY sub-blocks in the block. Each XY sub-block for which the memory operation is performed has its NAND strings connected to a different set of contiguous bit lines. In an aspect the memory operation is a program operation with selected memory cells in each of the multiple XY sub-blocks programmed in parallel while inhibiting programming of all memory cells in all other XY sub-blocks in the block. In one aspect, the memory operation is an erase operation.