QLC Memory Bit Segmentation for Reliable Error Correction
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Solution Overview
Problem
Existing memory systems face challenges in effectively utilizing the full storage capacity of Quad-Level Cells (QLC) due to narrow reading windows and reliance on low-density parity-check codes (LDPC) for error correction, leading to errors and reduced reading performance when error bits exceed a certain threshold.
Innovation Solution
A memory system design where memory cells are divided into first and second types of bits, with the first type storing valid data and the second type storing check data obtained through error correction encoding, enabling effective error correction by utilizing the check data during reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If QLC memory cells are used to increase storage density, then storage capacity is improved, but reading reliability deteriorates due to narrow reading windows
Solution Approach 1:
The patent divides each QLC memory cell into multiple bit positions (first bit position and second bit position) with different functions. The first bit position stores valid data while the second bit position stores check data, segmenting the storage function to simultaneously achieve high density and improved error correction capability.
Solution Approach 2:
Different bit positions within the same QLC memory cell are assigned different qualities/functions. The first bit position is optimized for data storage while the second bit position is optimized for error detection and correction, allowing each portion to perform its specific function with high reliability.
2Reliability
If LDPC error correction is used to correct errors, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The error correction function is segmented into two parts: check bits generated by simple parity check logic and check bits generated by LDPC encoding. This segmentation allows the system to use lightweight parity checks for common cases while reserving LDPC for more complex error scenarios, reducing overall complexity.
Solution Approach 2:
Instead of applying full LDPC encoding to all data, the patent uses partial action by generating check bits only for specific bit positions and using simple parity checks where sufficient, applying LDPC only when necessary to achieve error correction with reduced computational overhead.
3Quantity of substance
If all memory bits are used to store valid data to maximize capacity, then storage density is improved, but error correction capability deteriorates
Solution Approach 1:
The patent applies local quality by assigning different functions to different bit positions within the same memory cell. Specific bit positions are designated for check data storage with different encoding schemes (parity check vs. LDPC), allowing the system to maintain high overall density while providing targeted error correction where most needed.
Data Source
AI summary
An example memory system includes a memory device and a memory controller coupled to the memory device. The memory device may include memory cells having a memory bit count of multiple bits, the memory cells include first and second types of memory bits, the first type of memory bits are used to store valid data, the second type of memory bits are used to store first type of check data, and the first type of check data is obtained by performing error correction encoding on the valid data stored in the first type of memory bits. The memory controller is configured to: perform error correction on the valid data in which an error occurs by at least using the first type of check data in the second type of memory bits when the error occurs in reading the valid data in the first type of memory bits.