Semiconductor Memory Node Routing for Stacked Cell Selection
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently managing the electrical connections and operations within stacked memory cells, particularly in terms of addressing select transistors and gate lines, which affect the performance and efficiency of read, write, and erase operations.
Innovation Solution
The semiconductor memory device incorporates a memory cell array with a peripheral circuit that includes a charging circuit, discharging circuit, address select circuit, and amplifier circuits, along with first transistors and via electrodes, to manage electrical conductivity and operations between nodes, enabling precise control of memory cell selection and data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in a direction intersecting with the substrate surface to increase storage density, then the quantity of memory cells increases, but the complexity of electrical connections and control between stacked cells increases
Solution Approach 1:
The memory cell array is divided into multiple blocks (first block, second block, etc.), with each block containing stacked memory cells. This segmentation allows independent control and connection management for each block, reducing the overall complexity of electrical connections while maintaining high storage density through vertical stacking.
Solution Approach 2:
The patent transitions from planar memory cell arrangement to three-dimensional vertical stacking. Memory cells are arranged in multiple layers along the vertical direction intersecting the substrate surface, enabling increased storage capacity without proportionally increasing connection complexity through systematic layer management.
2Measurement precision
If multiple select transistors and gate lines are added to control stacked memory cells, then the precision of memory cell selection improves, but the number of components and wiring increases
Solution Approach 1:
Gate lines are designed to serve multiple functions across different memory cell blocks. The same gate line structure can selectively control memory cells in different blocks by applying appropriate voltages, reducing the total number of gate lines needed while maintaining precise selection capability through systematic voltage control.
Solution Approach 2:
Select transistors act as intermediary components between gate lines and memory cells. These transistors provide precise control by acting as switches that can independently enable or disable access to specific memory cells or blocks, achieving high selection precision without requiring a separate direct connection for each memory cell.
3Reliability
If more via electrodes and nodes are used to connect stacked memory cells, then the reliability of electrical connections improves, but the manufacturing complexity and device size increase
Solution Approach 1:
Multiple via electrodes are strategically merged and shared between adjacent memory cell blocks and layers. Common via electrodes serve multiple connection purposes, reducing the total number of via electrodes required while maintaining reliable electrical connections through optimized placement and shared infrastructure.
Solution Approach 2:
Nodes are designed to serve multiple connection functions across different memory cell blocks and circuit components. A single node can connect multiple via electrodes and serve as a common electrical junction for several memory cells, reducing the total number of nodes needed while ensuring reliable electrical connectivity.
Data Source
AI summary
A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.