Stacked Vertical Transistor Semiconductor Memory for Low-Power Retention
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing area, power consumption, and data retention after power interruption, particularly in volatile and non-volatile memory devices.
Innovation Solution
A semiconductor device design incorporating a first transistor, a second transistor, and a capacitor, where the second transistor and capacitor are stacked over the first transistor, utilizing a wide band gap oxide semiconductor for the second transistor to reduce off-state current, and sharing manufacturing processes to minimize area and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a DRAM is used to reduce area, then area is reduced, but data retention period becomes extremely short and power consumption cannot be sufficiently reduced
Solution Approach 1:
The patent changes the material parameter of the transistor channel from conventional silicon to oxide semiconductor, which has fundamentally different electrical characteristics including extremely high off-state resistance. This parameter change enables both long data retention period and low power consumption while maintaining small area.
2Speed
If an SRAM is used to operate at high speed, then speed is improved, but area becomes large and power consumption during data retention period cannot be sufficiently reduced
Solution Approach 1:
The patent changes the transistor material parameter from silicon to oxide semiconductor, achieving extremely high off-state resistance that enables low power consumption during data retention. The simplified 1T1C structure reduces area compared to conventional 6T SRAM while maintaining high speed operation through the fast switching capability of oxide semiconductor transistors.
3Duration of action of stationary object
If a flash memory is used to hold data with semi-permanent retention, then data retention is improved, but power consumption increases due to high voltage requirements
Solution Approach 1:
The patent changes the transistor material from conventional silicon to oxide semiconductor with wide band gap, enabling operation at low voltage without requiring high voltage for data retention. The oxide semiconductor transistor maintains extremely high off-state resistance at low voltage, eliminating the need for high voltage pulses while achieving long data retention period.
4Area of stationary object
If transistor miniaturization is performed to reduce area, then area is reduced, but off-state current increases
Solution Approach 1:
The patent changes the material parameter from silicon to oxide semiconductor, which has inherently higher off-state resistance even at miniaturized dimensions. The oxide semiconductor material maintains excellent off-state characteristics despite size reduction, actually improving the area-to-offstate-current ratio compared to conventional silicon transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a semiconductor device with reduced area, low power consumption, and the ability to retain data after power interruption, enabling high integration and efficient data storage.
Implementation Method 1
a transistor formed using an oxide semiconductor with a wide band gap has significantly high off-state resistance
Data Source
AI summary
A semiconductor device is described, which includes a first transistor, a second transistor, and a capacitor. The second transistor and the capacitor are provided over the first transistor so as to overlap with a gate of the first transistor. A semiconductor layer of the second transistor and a dielectric layer of the capacitor are directly connected to the gate of the first transistor. The second transistor is a vertical transistor, where its channel direction is perpendicular to an upper surface of a semiconductor layer of the first transistor.