3D Vertical Interconnect Architecture for Faster Logic-Memory Access
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current logic and memory circuits face bottlenecks in storage and retrieval times due to increased computational demands in machine learning systems, where parallel arrangements of devices lead to inefficiencies in data access.
Innovation Solution
The method involves forming a multiple die stack with a power delivery network (PDN) layer and silicon interposers to create vertical connections between logic and memory devices, reducing interconnect distance and enhancing connection density through hybrid bonding and chemical mechanical polishing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If parallel arrangement of logic and memory devices is used, then device complexity is reduced, but storage and retrieval time increases
Solution Approach 1:
The patent transitions from a two-dimensional parallel arrangement of logic and memory devices to a three-dimensional vertical stack configuration. Multiple dies are stacked vertically with interposer layers, creating vertical interconnect paths that reduce RC delay and improve data access speed while maintaining integration density.
2Length of stationary object
If vertical die stacking is implemented, then interconnect distance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent introduces interposer layers as intermediary structures between stacked dies. These interposer layers provide alignment references, mechanical support, and electrical interconnects, enabling precise registration of vertical die stacks while accommodating manufacturing tolerances in hybrid bonding processes.
3Quantity of substance
If hybrid bonding process is used, then connection density is increased, but process complexity increases
Solution Approach 1:
The patent performs preliminary preparation of bonding surfaces including forming alignment marks, patterned metal interconnect layers, and controlled roughness features before the hybrid bonding process. This pre-processing enables higher connection density through precise alignment while simplifying the actual bonding step by having all critical features pre-established.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces RC delay by up to 100 times, enabling faster data storage and retrieval, and supports increased processing speeds in machine learning systems by minimizing interconnect distance and increasing connection density.
Implementation Method 1
performing a first chemical mechanical polishing (CMP) process or a first etching process on the first circuit wafer to remove the first circuit support layer
Implementation Method 2
performing a second CMP process or a second etching process on the interposer support layer
Implementation Method 3
hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections
Data Source
AI summary
In some embodiments, a method for forming a multiple die stack comprises forming a first circuit wafer with multiple first circuit dies and a first circuit support layer on a bottom of the first circuit wafer where each first circuit die has a power and circuit layer underlying a power and signal layer, forming an interposer wafer with multiple interposer dies and an interposer support layer on a top of the interposer wafer where each interposer die has a power and signal layer underlying a power via and signal via layer, and hybrid bonding a top surface of the first circuit wafer to a bottom surface of the interposer wafer to form a first bonded wafer with electrical power and signal connections between the multiple first circuit dies and the multiple interposer dies where the interposer wafer provides structural support of the first bonded wafer during subsequent processing.