3D Vertical Memory Metal Gate Replacement Process
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Solution Overview
Problem
Current 3-D vertical memory technologies face challenges in scaling down memory sizes due to crosstalk issues and high RC values, leading to increased costs and complex processes, with existing technologies either limiting metal material usage in control gates or source lines, affecting electrical performance.
Innovation Solution
A method for manufacturing 3-D vertical memory devices that forms metal control gates and source lines using a replacement process, integrating metal materials to reduce RC values and improve electrical performance, by forming a multilayer structure with insulating and sacrificial layers, creating through holes, and replacing sacrificial layers with metal to form interconnected channel structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal materials are used for control gates, then RC values are reduced and electrical performance is improved, but manufacturing complexity increases due to process compatibility issues
Solution Approach 1:
The control gate is divided into multiple stacked segments (first control gate, second control gate, etc.) that can be independently formed and replaced with metal materials. This segmentation allows selective metalization of control gates while maintaining compatibility with existing manufacturing processes, thereby reducing RC values without requiring complete process overhaul.
Solution Approach 2:
A sacrificial layer is introduced as an intermediary material during the manufacturing process. This sacrificial layer is temporarily deposited to define the control gate structure, then replaced with metal materials through a controlled replacement process. The sacrificial layer acts as a mediator that enables metal control gate formation while maintaining process compatibility with existing fabrication tools and methods.
2Area of moving object
If memory cell size is scaled down in planar structure, then integration density is improved, but crosstalk between adjacent memory units increases
Solution Approach 1:
The memory structure transitions from a planar two-dimensional layout to a three-dimensional vertical stacked architecture. Multiple control gates are stacked vertically above each other, allowing memory cells to be arranged in three dimensions. This dimensional change enables significant reduction in memory cell footprint area while the vertical separation between cells reduces parasitic coupling and crosstalk effects that plague scaled-down planar structures.
3Ease of manufacture
If conventional photolithographic tools are used, then manufacturing cost is reduced, but manufacturing precision deteriorates for critical dimensions below 40 nm
Solution Approach 1:
The control gate formation process is segmented into multiple steps using standard photolithographic tools. Instead of requiring a single high-precision step, the process divides pattern formation into sequential operations that can be performed with existing tools, maintaining cost-effectiveness while achieving the required precision through cumulative process control.
Solution Approach 2:
Sacrificial layers are deposited and patterned in advance using conventional photolithographic tools before the actual metal control gate formation. This preliminary action prepares the structure with appropriate dimensions and geometry using existing tools, then subsequent replacement processes achieve the final high-precision metal structures without requiring expensive next-generation lithography equipment.
Data Source
AI summary
A novel method for manufacturing a 3-D vertical memory comprising the steps of dividing a multilayer structure composed of insulating intermediate layers and sacrificial intermediate layers into a first multilayer structure and a second multilayer structure, replacing the sacrificial intermediate layers in the multilayer structures with metal intermediate layers, and manufacturing the channel structure in two multilayer structures.