3D Vertical NAND String Fabrication via Sacrificial Etching
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Solution Overview
Problem
Current three-dimensional non-volatile memory devices face challenges in efficiently forming monolithic three-dimensional NAND string memory devices with high density and complexity, particularly in creating vertical NAND strings with multiple memory levels over a single substrate without intervening substrates.
Innovation Solution
The method involves forming a monolithic three-dimensional NAND string memory device by creating a stack of alternating insulating and conductive layers over a semiconductor substrate, using sacrificial material layers that are selectively etched to form memory openings, and then filling these openings with semiconductor channels and dielectric cores, followed by the formation of control gate electrodes and charge storage elements, allowing for the integration of multiple memory levels without separate substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory levels are integrated over a single substrate, then storage density is improved, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory structures to three-dimensional vertical stacking, where multiple memory levels are stacked vertically over a single substrate. This dimensional change enables high storage density by utilizing the vertical space above the substrate rather than expanding horizontally, allowing multiple memory cells to be integrated in the Z-direction while maintaining a compact footprint.
Solution Approach 2:
The patent implements a nested structure where memory cells are arranged in vertical columns with control gates, charge storage elements, and tunnel dielectrics nested concentrically around a central semiconductor channel. Multiple such columns are then stacked vertically, creating a nested arrangement where each memory level contains nested functional elements, enabling high integration density within a compact three-dimensional structure.
2Quantity of substance
If vertical NAND strings with multiple memory levels are formed, then storage capacity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the vertical NAND string into discrete functional segments including tunnel dielectric layers, charge storage elements, blocking dielectric layers, and control gate electrodes, with each segment formed through separate deposition and patterning steps. This segmentation allows precise control over the thickness and composition of each layer, enabling accurate formation of multiple memory levels while maintaining manufacturing precision through standardized repetitive processes.
Solution Approach 2:
The patent forms sacrificial material layers and templates in advance before creating the final memory structure. These preliminary structures guide the subsequent formation of semiconductor channels, dielectric cores, and charge storage elements, ensuring precise alignment and positioning. The sacrificial materials are removed after serving their templating function, leaving behind the precisely formed vertical NAND string structure with multiple memory levels.
Data Source
Figure 1
Figure 2A~4B
Figure 5A~6C
AI summary
A memory device includes a plurality of memory cells arranged in a string substantially perpendicular to the major surface of the substrate (10) in a plurality of device levels, at least one first select gate electrode located between the major surface of the substrate and the plurality of memory cells, at least one second select gate electrode located above the plurality of memory cells, a semiconductor channel (601) having a portion that extends vertically along a direction perpendicular to the major surface, a first memory film (54) contacting a first side of the semiconductor channel, and a second memory film (54) contacting a second side of the semiconductor channel. The second memory film is electrically isolated from the first memory film, and is located at a same level as the first memory film.