3D Wafer Interconnect Layout for Shorter DMA Data Paths
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Solution Overview
Problem
Existing 3D wafer-level packaging technologies face challenges in efficiently managing data transmission across multiple layers, leading to long transmission distances and inefficiencies due to the need for data to traverse multiple integrated circuit components.
Innovation Solution
Implementing a 3D interconnected data flow architecture with through-silicon vias, re-distribution layers, and hybrid bonding to interconnect three wafer layers, including a direct memory access master controller in one of the layers to facilitate direct data transmission without crossing all layers, thereby reducing transmission distance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of stationary object
If data transmission traverses multiple wafer layers in traditional 3D packaging, then multi-layer integration is achieved, but transmission distance increases and efficiency decreases
Solution Approach 1:
The patent transitions from traditional vertical stacking to a 3D interconnected architecture where wafer layers are connected through multiple dimensions using through-silicon vias and re-distribution layers. This dimensional change enables shorter transmission paths by allowing data to travel through intermediate connection points rather than traversing the entire vertical distance across multiple layers.
Solution Approach 2:
The patent introduces through-silicon vias, re-distribution layers, and hybrid bonding interfaces as intermediary elements that facilitate data transmission between wafer layers. These intermediaries provide multiple connection points and pathways, allowing data to be transmitted more efficiently by routing through optimal paths rather than direct long-distance traversal.
2Quantity of substance
If wafer layers are stacked vertically to increase storage capacity, then on-chip storage capacity increases, but data transmission distance increases
Solution Approach 1:
The patent segments the data transmission path into multiple short segments using through-silicon vias and re-distribution layers. Instead of a single long transmission path across stacked layers, data is transmitted through multiple shorter segments connected via intermediate layers, reducing the overall transmission distance while maintaining multi-layer storage capacity.
Solution Approach 2:
The patent implements a nested structure where through-silicon vias are embedded within wafer layers, and re-distribution layers are integrated between functional layers. This nesting allows multiple storage layers to be packed vertically while providing intermediate access points that reduce transmission distances to and from each storage layer.
3Ease of manufacture
If traditional interconnection methods are used, then manufacturing is simpler, but transmission efficiency is lower
Solution Approach 1:
The patent merges multiple interconnection techniques (through-silicon vias, re-distribution layers, and hybrid bonding) into a unified 3D interconnected architecture. This combination achieves high transmission efficiency by providing multiple short transmission paths while remaining manufacturable through established semiconductor fabrication processes.
Data Source
AI summary
Embodiments of the present disclosure provide an integrated circuit component, a processor, and a system on chip. The integrated circuit component includes three wafer layers. Each of the wafer layers includes a front side and a back side. The front side of a first wafer layer and the front side of a second wafer layer are stacked, and the front side of the second wafer layer and the back side of a third wafer layer are stacked. The three wafer layers are interconnected through a through-silicon via, a re-distribution layer, and hybrid bonding. The second wafer layer or a slow wafer layer among the three wafer layers includes a direct memory access master controller. The direct memory access master controller is configured to receive a data transmission request sent by a slave terminal of another wafer layer, and cause a slave terminal of the second wafer layer or the slow wafer layer among the three wafer layers to perform data transmission.