3D Wafer Stack Redistribution Layer for Functional Die Bypass

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Solution Overview

Problem

Current semiconductor technologies face challenges in maximizing functional yield in 3D wafer stacks due to limitations in connecting functional die sites while bypassing non-functional sites, leading to inefficiencies in power management and interconnection density.

Innovation Solution

A customized redistribution layer is introduced between each semiconductor wafer in a 3D stack, electrically connecting functional die sites while bypassing non-functional sites, utilizing tested wafer maps to optimize connections and reduce redundant circuit overhead.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional bonding techniques are used to stack semiconductor wafers, then the wafer stack can be formed, but non-functional die sites cannot be bypassed leading to reduced functional yield

Engineering Contradiction:

Improvefunctional yieldVSAvoidinterconnection structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

A redistribution layer is introduced as an intermediary component between stacked semiconductor wafers. This redistribution layer selectively connects functional die sites while bypassing non-functional ones, thereby improving functional yield without requiring changes to the core wafer stacking process

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The redistribution layer is configured with locally differentiated connectivity: it provides electrical connections to functional die sites while intentionally omitting connections to non-functional die sites. This local quality differentiation enables selective bypassing of defective areas

Inventive Principle:

Principle #3Local quality

2Use of energy by moving object

If all die sites are connected in traditional stacking, then interconnection density is maximized, but power is wasted in non-functional circuits

Engineering Contradiction:

Improvepower consumptionVSAvoidinterconnection density

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The redistribution layer extracts and removes connections to non-functional die sites from the interconnection structure. By taking out these redundant connections, power consumption is reduced without significantly impacting the overall interconnection density among functional circuits

Inventive Principle:

Principle #2Taking out (Extraction)

3Quantity of substance

If minimum feature size is reduced to increase integration density, then more components fit in given area, but manufacturing precision requirements increase

Engineering Contradiction:

Improveintegration densityVSAvoidfeature size control

Core Design Contradiction:

Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent transitions from two-dimensional planar integration to three-dimensional stacked architecture. By adding the vertical dimension with multiple wafer layers and a redistribution layer, integration density is dramatically increased without requiring further reduction of minimum feature sizes in the lateral plane

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250022800A1Three-dimensional chip or wafer stack

Publication Date: 2025.01.16 INTERNATIONAL BUSINESS MACHINE CORPORATION

AI summary

A 3D chip (or wafer) stack is provided in which a customized redistribution layer is located between each semiconductor wafer of the chip (or wafer) stack. The customized redistribution layer connects functional die sites on a first semiconductor wafer to functional die sites on a second semiconductor wafer, while by-passing non-functional die sites on the second semiconductor wafer.