3D Memory Word Line Segmentation for Dense Array Stability

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Solution Overview

Problem

Existing semiconductor memory technologies face challenges in achieving high memory cell density while preventing structural instability due to high aspect ratios during the formation of word lines and bit lines, leading to issues such as twisting or collapsing of features.

Innovation Solution

A multiple-patterning process is employed to form word lines and transistors in a semiconductor memory array, involving two separate patterning steps to reduce the aspect ratio and prevent structural instability, allowing for improved memory cell density and stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a single patterning process is used to form word lines and bit lines, then the manufacturing process is simpler, but the aspect ratio becomes too high causing structural instability and twisting or collapsing of features

Engineering Contradiction:
Improvepatterning process simplicityVSAvoidstructural stability of word lines and bit lines
Core Design Contradiction:
Ease of manufactureVSStability of the object's composition

Solution Approach 1:

The patterning process is divided into multiple separate patterning steps instead of attempting to form all word lines and bit lines in a single step. This segmentation allows each patterning operation to work with lower aspect ratios, preventing structural collapse while maintaining manufacturing feasibility through systematic multi-step processing

Inventive Principle:
Principle #1Segmentation

2Quantity of substance

If memory cell density is increased, then more data can be stored, but the aspect ratio of features increases leading to twisting or collapsing during formation

Engineering Contradiction:
Improvememory cell densityVSAvoidstructural stability during feature formation
Core Design Contradiction:
Quantity of substanceVSStability of the object's composition

Solution Approach 1:

By dividing the patterning into multiple steps, each step can achieve higher local density without creating excessively high aspect ratios that would cause structural failure. The segmented approach allows dense packing of memory cells while maintaining structural integrity through controlled, sequential feature formation

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent employs three-dimensional stacking of memory cells with alternating orientations (e.g., first set of cells oriented in one direction, second set in perpendicular direction). This dimensional arrangement increases storage density while distributing aspect ratio challenges across multiple layers and orientations, preventing structural collapse in any single dimension

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250365971A1Three-dimensional memory device and method
Publication Date: 2025.11.27 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250365971A1 patent drawing
  • US20250365971A1 patent drawing
  • US20250365971A1 patent drawing

AI summary

A semiconductor device and method of manufacture are provided. In embodiments a memory array is formed by manufacturing portions of a word line during different and separate processes, thereby allowing the portions formed first to act as a structural support during later processes that would otherwise cause undesired damage to the structures.