Digital Storage TRIZ Cases

Offset cancellation during charge sharing improves sensing margin and cuts bit line sensing time without a separate pre-charge circuit.

Two-stage DCA clock training uses 180° and 90°/270° phase codes to widen read margin while cutting training delay in high-speed memory.

Analog interface circuits transfer integrated column currents directly to the next memory-cell row, cutting ADC area, power, and delay.

Location detection circuits assign and store die identifiers, enabling individual access to grouped memory dies on a shared bus.

A sense-amplifier flip-flop uses ferroelectric storage to retain data at low VDD while cutting leakage, area, and restore power.

A master-slave flip-flop and DOUT window controller screen weak bitcells and narrow read-output toggling without added latency.

Weights stored in resistive memory cells enable parallel transformer computation, cutting serial data transfer and speeding inference.

Address pins are latched during initial I2C addressing, then reused for status signaling to cut pin count in small secondary devices.

Sequential delay training aligns data and strobe timing to reduce random skew, increase timing margin, and improve semiconductor reliability.

Charge injection on paired bitlines cancels sense amplifier offset voltage, improving sensing margin and accurate memory reads.

Internal sync signals and per-core delay compensation align multiple DAC outputs on one clock edge, reducing jitter and clock complexity.

A recessed spin-orbit torque wiring region lets ion beams clean ferromagnetic sidewalls without reattaching conductive residue or degrading magnetic behavior.

Segmented pull-up and pull-down buffers cut data I/O terminal capacitance, boosting DRAM transfer speed and lowering current use.

Centrosymmetric pass-gate and transistor placement makes dual-port read paths more symmetric, stabilizing PMOS behavior and read speed.

Series mergers and an aligner delay read-data edges to manage skew and cut latency as memory arrays grow on mixed-function chips.

Digital phase alignment using Josephson-junction counters enables precise low-power chip links across cryogenic and warmer IC domains.

Closed-loop clock correction aligns 90-degree memory timing by jointly compensating phase skew and duty cycle errors.

Written and read data comparison verifies duty cycle adjuster validity when picosecond-level correction is too small to observe directly.

RRAM placed at SRAM storage-node drains enables non-volatile retention while preserving fast access, low voltage, and low power.

Time-domain edge delay accumulation replaces voltage readout in CIM memory, improving signal margin, MAC accuracy, and power use.

Non-volatile RRAM configuration bits replace SRAM in FPGA routing to cut power and size while improving radiation immunity and power-up speed.

Integrated magnetic stacks and shared conductive regions simplify XNOR and OR operations, cutting circuit complexity and power use.

A folded comparator with switched input paths and cross-coupled regeneration cuts ISI in high-speed serial links while supporting lower supply voltages.

A bank-level delay circuit aligns asynchronous and command signal timing across memory banks to improve internal test accuracy.

Segmented sub-arrays with local-global bit-line charge sharing improve multi-bit weight precision and matrix-vector throughput in analog SRAM computing.

Interleaving multibit symbols across DIMM codewords improves chipkill-style error correction on 16-bit buses while reducing latency.

A reset-before-write latch with input termination and read sensing cuts FPGA configuration memory area while preserving readable, stable data.

A DDR PAM4 feedback circuit uses latch-based DFE and multi-tap correction to reduce inter-symbol interference and improve memory signal detection.

PTAT and CTAT RC delay elements offset temperature drift to keep ZQ calibration and memory timing stable across operating ranges.

Concurrent duty-cycle monitoring trains data and read clocks together, reducing memory clock training time while correcting read-clock offset.

Single flux quantum pulses set a bi-stable storage loop current, enabling fast, low-power superconducting memory readout.

Adaptive capacitance and equalization in a memory receiving circuit reduce input capacitance and noise to improve jitter and bit error rate.

DC-converted phase comparison detects multiphase clock skew and drives delay codes to preserve signal quality at high data speeds.

A driver circuit and parallel transistor reduce input clock slew to avoid early reset and preserve reliable internal clock generation.

A phase-shifted reception clock uses period counting and delay control to keep parallel data aligned across SDR, DDR, and QDR links.

A resistor turns spike currents into steady output current, improving magnetization switching stability in spin-charge conversion logic.

Adjustable delay control shifts word line timing based on voltage swing, preserving pulse width and memory circuit reliability.

Switching between external and internal read clocks preserves data latching during duty cycle adjustment while reducing CPU power use.

A main and auxiliary DAC phase interpolator cuts phase and amplitude errors, reducing AM-to-PM distortion in high-frequency memory timing.

PCM cells act as both storage and logic gates, cutting CPU-memory data transfer to improve computing speed and energy efficiency.

A dual-path read clock with selector avoids data latching errors caused by duty cycle distortion during memory clock adjustment.

Switching a memory clock buffer between bypass, single-PLL, and dual-PLL modes cuts power and thermal load across DDR speeds.

Active inductors in an OTA circuit improve DDR5 duty cycle characteristics and bandwidth while avoiding the large area of passive inductors.

Replica SRAM latches track PFET and NFET threshold shifts to set a retention supply voltage that cuts low-power SRAM energy use.

Adaptive equalization switches signal-pair selection by feedback to curb intersymbol interference while lowering receiver power use.

Precharge transistors and capacitors hold amplifier inputs at low constant levels, keeping the current source saturated for faster ZQ comparison.

A spin-transfer element paired with a nano-SQUID cuts cryogenic memory power use while enabling fast, high-density readout compatible with RSFQ signals.

A common receiving driver shares one differential clock across memory sub-channels, cutting interface power while preserving independent sampling.

A selectable processed-signal path removes narrow pulses from DRAM external signals, improving signal accuracy under interference.

A shared differential clock with chip-select gating lets memory sub-channels run independently while cutting interface power and complexity.