Duty Cycle Adjuster Circuit Testing via Write-Read Data Comparison
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Solution Overview
Problem
The existing duty cycle adjuster (DCA) circuit in semiconductor memory chips has a limited deviation correction amplitude and minimum holding time, making it difficult to determine whether the circuit is in a valid state due to small correction amplitude and short data retention time on the data bus.
Innovation Solution
A method and apparatus for testing the DCA circuit by adjusting initial read/write clock signals with duty cycle deviations, performing write and read operations at a specified storage address, and generating a test result based on the written and read data to accurately determine the circuit's validity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a duty cycle adjuster (DCA) circuit is used to correct duty cycle deviation, then the duty cycle can be adjusted, but the deviation correction amplitude is relatively small (only a dozen of picoseconds) making it difficult to observe whether the circuit is in a valid state
Solution Approach 1:
The patent transforms the measurement from the time domain (direct observation of picosecond-level duty cycle correction) to the data domain (comparing written and read data). By dimensionally changing the observation space, the measurement becomes feasible with standard equipment while maintaining high precision.
Solution Approach 2:
The patent introduces data as an intermediary medium to indirectly measure the DCA circuit's validity. Instead of directly observing the tiny time deviation, the circuit's effect is manifested through data integrity, which serves as a measurable proxy for circuit performance.
2Reliability
If the minimum holding time of data on the data bus is hundreds of picoseconds, then data retention is ensured, but the small correction amplitude of the DCA circuit (a dozen of picoseconds) becomes even harder to detect against the longer time scale
Solution Approach 1:
The patent replaces direct temporal measurement (mechanical/time-based observation) with data comparison (logical/state-based observation). This substitution allows precise measurement of tiny time deviations by translating them into detectable data state changes, bypassing the limitation of direct time-scale measurement.
Solution Approach 2:
The patent changes the measurement parameter from time duration (picoseconds) to data state (valid/invalid). By transforming the parameter being measured, the system can detect small duty cycle deviations through their cumulative effect on data integrity rather than attempting to measure the tiny time difference directly.
Data Source
AI summary
A method and an apparatus for testing an adjustment circuit is applied to a test platform. The adjustment circuit includes a duty cycle adjuster (DCA) circuit. The method includes: receiving written data at a specified storage address based on a first read/write clock signal; and receiving read data from the specified storage address based on a second read/write clock signal, and generating a test result of the DCA circuit based on the written data and the read data; wherein the DCA circuit is configured to adjust a first initial read/write clock signal to generate the first read/write clock signal and/or adjust a second initial read/write clock signal to generate the second read/write clock signal, and a duty cycle of the first initial read/write clock signal and/or a duty cycle of the second initial read/write clock signal have/has a first deviation.